[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-81926-en":3,"doc-seo-81926-105":29,"detail-sidebar-cat-0-en-105":90},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":13,"seo_description":14,"update_tm":27,"read_time":28},81926,8796095461564,"Liam","https://ap-avatar.wpscdn.com/davatar_155a257f0dc6eb9ab79c44ca47cae57d",8,"Research & Report","Optimizing ML Workload Partitioning between CPUs and CIM Accelerators for Heterogeneous Computing","Computing-in-Memory (CIM) accelerators run matrix-vector multiplications (MVMs) in memory, making them attractive for machine learning inference. Existing CIM workload partitioning methods often overlook RRAM constraints including limited memory, high write latency, and limited endurance, and they neglect parallelism, low-level architectural effects, and the role of the host CPU. An Integer Linear Programming (ILP) framework optimizes end-to-end inference latency for heterogeneous CPU–CIM systems by combining empirical profiling with analytical models under RRAM constraints. Results report up to 30.9× and 7.3× speedups.","PREPRINT -Accepted for publication at the 34th IFIP/IEEE International Conference on Very Large Scale Integration SoC (VLSI-SoC),  \nOctober 11–14, 2026, in Limassol, Cyprus.  \n©2026 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.  \nOptimizing ML Workload Partitioning between CPUsand CIM Accelerators for Heterogeneous Computing  \nJoel Klein, Rebecca Pelke, Roberto Laudani, Jan Moritz Joseph, Rainer Leupers  \nInstitute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany {klein, pelke, laudani, joseph, [leupers}@ice.rwth-aachen.de](leupers}@ice.rwth-aachen.de)  \narXiv :2607 .05240v 1 [ cs .ET] 6 Jul 2026  \nAbstract—Computing-in-Memory (CIM) accelerators execute Matrix-Vector Multiplications (MVMs) in memory, making thema compelling solution for Machine Learning (ML) workloads. However, existing ML workload partitioning approaches for CIM accelerators do not fully account for Resistive Random Access Memory (RRAM) constraints such as limited memory, high write latency, and limited endurance. They also neglect parallelism, low-level architectural effects, or the Central Processing Unit (CPU) as a complementary compute resource.  \nTo address these limitations, we propose an Integer Linear Programming (ILP)-based workload partitioning framework for heterogeneous CPU–CIM systems. It minimizes end-to-end inference latency under RRAM constraints, captures parallelism, and combines empirical profiling with analytical models. Using our framework, heterogeneous CPU–CIM execution achieves speedups of up to 30.9 × over CPU-only execution on an edge CPU and 7.3 × over a high-performance CPU. A Design Space Exploration (DSE) yields further design insights for future CIM accelerators.  \nIndex Terms—CIM, Heterogeneous Computing, Workload Partitioning, RRAM, ILP  \nI. INTRODUCTION  \nEfficient execution of Machine Learning (ML) workloads requires new hardware architectures. Computing-in-Memory (CIM) fuses computation and memory to address the von Neumann bottleneck [1], executing Matrix-Vector Multiplications (MVMs) with O(1) latency using crossbar arrays [2]–[4] . Resistive Random Access Memory (RRAM) is a promising CIM candidate due to its high device density, low power consumption, non-volatility, and CMOS compatibility [1], [5], [6] . However, CIM accelerators rely on a host Central Processing Unit (CPU) to execute unsupported operators, requiring workload partitioning between CPU and CIM accelerator [4] .  \nFurthermore, CIM storage is limited by the available crossbars [7] . Modern Convolutional Neural Networks (CNNs) often exceed this capacity [7]–[11] . Moreover, RRAM write latency and endurance limits make dynamic weight replacement impractical [5], [6], [12] . Hence, deployment requires static assignment of selected operators to the CIM accelerator.  \nExisting ML partitioning approaches [13]–[16] treat devices as black boxes, neglect low-level architectural characteristics or assume sequential execution. CIM-specific methods either assume full-model fit [17], [18] or rely on weight reprogramming [7],[11] . Furthermore, workload partitioning between the host CPU and the CIM accelerator remains an open problem.  \nThis work was funded by the Federal Ministry of Research, Technology and Space, Germany, in the project NeuroSys II (03ZU2106CA) .  \nIII Design Space Exploration   \nFig. 1: Overview of the proposed partitioning framework  \nWe propose a system-level workload partitioning framework for heterogeneous CPU–CIM systems. It covers latency characterization and static operator assignment. The resulting partitioning between CPU and CIM achieves up to 30.9 × and 7.3 × speedup over CPU-only","cbCaittJA0PF8kGo","https://ap.wps.com/l/cbCaittJA0PF8kGo","pdf",433187,1,5,"English","en",105,"# Introduction\n# Background\n## RRAM-based CIM Accelerators\n## Integer Linear Programming Concepts\n# Design Space Exploration\n# Framework Overview\n# Results and DSE\n# Conclusion","[{\"question\":\"Why is workload partitioning needed between the CPU and CIM accelerators?\",\"answer\":\"CIM accelerators support only a limited set of operators, so unsupported operations must be executed on the host CPU. Static operator assignment is therefore required for heterogeneous CPU–CIM execution.\"},{\"question\":\"What RRAM-related constraints does the proposed approach account for?\",\"answer\":\"The framework models limited CIM memory capacity, high RRAM write latency, and limited device endurance. These factors make dynamic weight replacement impractical and must be considered during partitioning.\"},{\"question\":\"How does the proposed ILP framework optimize inference performance?\",\"answer\":\"It minimizes end-to-end inference latency while enforcing RRAM constraints, operator support, and parallelism limits. It integrates empirical profiling with analytical performance models to choose an optimal static assignment.\"}]",1784177086,13,{"code":4,"msg":30,"data":31},"ok",{"site_id":24,"language":23,"slug":32,"title":13,"keywords":33,"description":14,"schema_data":34,"social_meta":85,"head_meta":87,"extra_data":89,"updated_unix":27},"optimizing-ml-workload-partitioning-between-cpus-and-cim-accelerators-for-heterogeneous-computing","",{"@graph":35,"@context":84},[36,53,67],{"@type":37,"itemListElement":38},"BreadcrumbList",[39,43,47,50],{"item":40,"name":41,"@type":42,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":44,"name":45,"@type":42,"position":46},"https://docshare.wps.com/document/","Document",2,{"item":48,"name":12,"@type":42,"position":49},"https://docshare.wps.com/document/research-report/",3,{"item":51,"name":13,"@type":42,"position":52},"https://docshare.wps.com/document/optimizing-ml-workload-partitioning-between-cpus-and-cim-accelerators-for-heterogeneous-computing/81926/",4,{"url":51,"name":13,"@type":54,"author":55,"headline":13,"publisher":57,"fileFormat":60,"inLanguage":23,"description":14,"dateModified":61,"datePublished":61,"encodingFormat":60,"isAccessibleForFree":62,"interactionStatistic":63},"DigitalDocument",{"name":9,"@type":56},"Person",{"url":40,"name":58,"@type":59},"DocShare","Organization","application/pdf","2026-07-16",true,{"@type":64,"interactionType":65,"userInteractionCount":4},"InteractionCounter",{"@type":66},"ViewAction",{"@type":68,"mainEntity":69},"FAQPage",[70,76,80],{"name":71,"@type":72,"acceptedAnswer":73},"Why is workload partitioning needed between the CPU and CIM accelerators?","Question",{"text":74,"@type":75},"CIM accelerators support only a limited set of operators, so unsupported operations must be executed on the host CPU. Static operator assignment is therefore required for heterogeneous CPU–CIM execution.","Answer",{"name":77,"@type":72,"acceptedAnswer":78},"What RRAM-related constraints does the proposed approach account for?",{"text":79,"@type":75},"The framework models limited CIM memory capacity, high RRAM write latency, and limited device endurance. These factors make dynamic weight replacement impractical and must be considered during partitioning.",{"name":81,"@type":72,"acceptedAnswer":82},"How does the proposed ILP framework optimize inference performance?",{"text":83,"@type":75},"It minimizes end-to-end inference latency while enforcing RRAM constraints, operator support, and parallelism limits. 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