[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-122284-en":3,"doc-seo-122284-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},122284,1099514067438,"River Wang","https://ap-avatar.wpscdn.com/avatar/100002539ee87300030?x-image-process=image/resize,m_fixed,w_180,h_180&k=1780474512215547542",8,"Research & Report","Novel Machine Learning Approach for Defect Detection in DFT Processes","Semiconductor testing faces rapidly rising complexity as IC device densities grow and defect mechanisms diversify beyond classic stuck-at faults. This paper reviews core DFT practices—scan-based structures, boundary scan, and built-in self-test (BIST)—and their use against logical fault models. It then explores machine learning methods, including support vector machines and neural networks, to accelerate test-pattern generation, strengthen bridging-fault coverage, and streamline board- or wafer-level screening. The work highlights how combining DFT and ML improves diagnostic accuracy while controlling testing costs.","Novel Machine Learning Approach for Defect Detection in  \nDFT Processes  \nVijayaprabhuvel Rajavel*  \nSemiconductor Design & Test Engineering Specialist, California, USA  \nEmail: [vijayscholarly@gmail.com](vijayscholarly@gmail.com)  \nAbstract  \nRecent advances in semiconductor technology have highlighted significant challenges in effectively testing modern integrated circuits (ICs) . As device densities increase and defect mechanisms become more diverse, conventional Design for Testability (DFT) methodologies – while indispensable – must contend with exponential growth in test complexity. This paper reviews the essential DFT practices, including scan-based structures, boundary scan, and built-in self-test (BIST), and examines how these practices address a variety of logical fault models. It further explores machine learning (ML) techniques as valuable tools for enhancing defect detection and diagnosis. By leveraging classification algorithms such as support vector machines and neural networks, ML-driven approaches can reduce test pattern generation time, improve bridging-fault coverage, and streamline board- or wafer-level screening. Collectively, this paper underscores how strategic synergy between DFT and ML can raise fault coverage, improve diagnostic precision, and contain testing costs in the face of ongoing technology scaling.  \nKeywords: Design for Testability (DFT); Machine Learning (ML); Scan Testing; Bridging Faults; Open/Short Defects; Built-In Self-Test (BIST); Automatic Test Pattern Generation (ATPG); Semiconductor Yield.  \n1. Introduction  \nDesign for Testability (DFT) encompasses a suite of architectural enhancements and methodologies – such asscan chains, built‑in self‑test (BIST), and boundary scan – that simplify the testing of integrated circuits (ICs) by improving internal observability and controllability while reducing the number of required test patterns [1, 2] . As semiconductor technologies advance into deep‑ and sub‑nanometer nodes, modern SoCs now integrate billions of transistors, rendering conventional testing approaches (e.g., deterministic automatic test pattern generation, ATPG) increasingly intractable due to near‑exponential growth in pattern‑generation complexity and fault‑diagnosis overhead [3] .  \nReceived: 2/27/2025  \nAccepted: 3/28/2025  \nPublished: 4/22/2025  \n* Corresponding author.  \nDriven by Moore’s Law [4], device scaling has also introduced a proliferation of subtle defect modes: besides classic stuck‑at faults, advanced processes exhibit open/short bridging failures, parametric drifts, and intermittent anomalies that can evade standard test vectors [5] . While augmented DFT techniques – such as boundary scan at the board level or in‑field BIST – capture a broader fault spectrum, they add significant area and timing overhead, may obscure complex failure signatures, and still rely on robust diagnostic algorithms to resolve ambiguous symptoms. Moreover, random‑pattern‑resistant or hard‑to‑detect faults demand highly targeted ATPG strategies to achieve acceptable coverage [1, 6] .  \nIn parallel, machine learning (ML) has emerged as a powerful tool in electronic design automation and data analytics [7, 8] . Initial applications in IC testing demonstrate substantial benefits: Roy and his colleagues [11] reported a 20–30 % reduction in PODEM backtracks – equating to roughly 25 % faster test‑pattern generation – when using neural‑network–guided heuristics; Huang and his colleagues [5] achieved up to 92 % accuracy in scan‑chain defect classification via support vector machines and multi‑stage ANNs; Xanthopoulos and his colleagues [14] improved wafer‑map die inking precision by applying RBF‑SVM clustering; and Sun and his colleagues [10] nearly doubled diagnostic resolution in volume diagnosis by merging syndrome data with statistical learning. These successes, however, depend on large volumes of accurately labeled failure logs, sensitive feature engineering (e.g., SCOAP metrics, logic depth","cbCairOMwIwzCByB","https://ap.wps.com/l/cbCairOMwIwzCByB","pdf",503758,1,10,"English","en",105,"# Introduction\n## DFT challenges under technology scaling\n## Defect diversity and limitations of deterministic ATPG\n## ML’s role in IC testing and practical constraints\n# Overview of contemporary DFT methods and the role of machine learning\n## Scan test and Automatic Test Pattern Generation (ATPG)\n## Built-In Self-Test (BIST)","[{\"question\":\"What DFT methods does the paper review for testing integrated circuits?\",\"answer\":\"It reviews scan-based structures, boundary scan, and built-in self-test (BIST) as key DFT practices to improve controllability and observability and to target logical fault models.\"},{\"question\":\"How does machine learning help defect detection in DFT processes?\",\"answer\":\"The paper explains that ML classification models such as support vector machines and neural networks can reduce test-pattern generation time, improve bridging-fault coverage, and streamline board- or wafer-level screening.\"},{\"question\":\"Why do conventional ATPG approaches become increasingly difficult as technology scales?\",\"answer\":\"As circuits grow to deep- and sub-nanometer nodes, pattern-generation complexity and diagnostic overhead rise near-exponentially, making deterministic ATPG computationally intractable.\"}]","Novel Machine Learning Approach for Defect Detection in DFT Processes | PDF",1785809818,25,{"code":4,"msg":31,"data":32},"ok",{"site_id":24,"language":23,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":86,"head_meta":88,"extra_data":90,"updated_unix":28},"novel-machine-learning-approach-for-defect-detection-in-dft-processes","",{"@graph":36,"@context":85},[37,54,68],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,48,51],{"item":41,"name":42,"@type":43,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":47},"https://docshare.wps.com/document/","Document",2,{"item":49,"name":12,"@type":43,"position":50},"https://docshare.wps.com/document/research-report/",3,{"item":52,"name":13,"@type":43,"position":53},"https://docshare.wps.com/document/novel-machine-learning-approach-for-defect-detection-in-dft-processes/122284/",4,{"url":52,"name":13,"@type":55,"author":56,"headline":13,"publisher":58,"fileFormat":61,"inLanguage":23,"description":14,"dateModified":62,"datePublished":62,"encodingFormat":61,"isAccessibleForFree":63,"interactionStatistic":64},"DigitalDocument",{"name":9,"@type":57},"Person",{"url":41,"name":59,"@type":60},"DocShare","Organization","application/pdf","2026-08-04",true,{"@type":65,"interactionType":66,"userInteractionCount":20},"InteractionCounter",{"@type":67},"ViewAction",{"@type":69,"mainEntity":70},"FAQPage",[71,77,81],{"name":72,"@type":73,"acceptedAnswer":74},"What DFT methods does the paper review for testing integrated circuits?","Question",{"text":75,"@type":76},"It reviews scan-based structures, boundary scan, and built-in self-test (BIST) as key DFT practices to improve controllability and observability and to target logical fault models.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"How does machine learning help defect detection in DFT processes?",{"text":80,"@type":76},"The paper explains that ML classification models such as support vector machines and neural networks can reduce test-pattern generation time, improve bridging-fault coverage, and streamline board- or wafer-level screening.",{"name":82,"@type":73,"acceptedAnswer":83},"Why do conventional ATPG approaches become increasingly difficult as technology scales?",{"text":84,"@type":76},"As circuits grow to deep- and sub-nanometer nodes, pattern-generation complexity and diagnostic overhead rise near-exponentially, making deterministic ATPG computationally intractable.","https://schema.org",{"og:url":52,"og:type":87,"og:title":13,"og:site_name":59,"og:description":14},"article",{"robots":89,"canonical":52},"index,follow",{"doc_id":7,"site_id":24},{"code":4,"msg":5,"data":92},[93,97,101,105,110,115,120,123,128,131,134],{"id":20,"doc_module":4,"doc_module_name":46,"category_name":94,"show_sort_weight":95,"slug":96},"Story & Novel",90,"story-novel",{"id":47,"doc_module":4,"doc_module_name":46,"category_name":98,"show_sort_weight":99,"slug":100},"Literature",80,"literature",{"id":53,"doc_module":4,"doc_module_name":46,"category_name":102,"show_sort_weight":103,"slug":104},"Exam",70,"exam",{"id":106,"doc_module":4,"doc_module_name":46,"category_name":107,"show_sort_weight":108,"slug":109},5,"Comic",60,"comic",{"id":111,"doc_module":4,"doc_module_name":46,"category_name":112,"show_sort_weight":113,"slug":114},6,"Technology",50,"technology",{"id":116,"doc_module":4,"doc_module_name":46,"category_name":117,"show_sort_weight":118,"slug":119},7,"Healthcare",40,"healthcare",{"id":11,"doc_module":4,"doc_module_name":46,"category_name":12,"show_sort_weight":121,"slug":122},30,"research-report",{"id":124,"doc_module":4,"doc_module_name":46,"category_name":125,"show_sort_weight":126,"slug":127},9,"Religion & Spirituality",20,"religion-spirituality",{"id":126,"doc_module":4,"doc_module_name":46,"category_name":129,"show_sort_weight":126,"slug":130},"World Cup","world-cup",{"id":21,"doc_module":4,"doc_module_name":46,"category_name":132,"show_sort_weight":21,"slug":133},"Lifestyle","lifestyle",{"id":135,"doc_module":4,"doc_module_name":46,"category_name":136,"show_sort_weight":106,"slug":137},19,"General","general"]