[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-123754-en":3,"doc-seo-123754-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},123754,1649267921044,"Ava Thompson","https://us-avatar.wpscdn.com/avatar/1800007509477c92dfb?_k=1782875107921204101",8,"Research & Report","Machine Learning System for Resource Prediction and Tool Options Optimization for Application-Specific Integrated Circuit (ASIC) Design - Thesis Report","The thesis develops machine learning models to predict key metrics in application-specific integrated circuit (ASIC) hardware design, reducing waste of computational resources. It addresses the operational challenge that memory requirements and resulting quality metrics are known only after jobs execute, while resource requests must be made in advance. Models are trained on experimental and real company project data, applying preprocessing and transformations to handle inconsistency and outliers. The final objective is a successful prediction model that improves scheduling decisions and minimizes costly mismatches in time and money.","MACHINE LEARNING SYSTEM FOR RESOURCE PREDICTION AND TOOL OPTIONS OPTIMIZATION FOR APPLICATION-SPECIFIC INTEGRATED CIRCUIT (ASIC) DESIGN  \nMARC GARCIA MASSANEDA  \nThesis supervisor: JONÀS CASANOVA BACHS (MARVELL TECHNOLOGY UK LTD SUCURSAL EN  \nESPAÑA)  \nTutor: JORDI CORTADELLA FORTUNY (Department of Computer Science) Degree: Bachelor's Degree in Data Science and Engineering  \nThesis report  \nFacultat d'informàtica de Barcelona (FIB)  \nEscola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona (ETSETB)  \nFacultat de Matemàtiques i Estadística (FME) Universitat Politècnica de Catalunya (UPC) -BarcelonaTech  \nAcknowledgements  \nMany people have helped me throughout the thesis. First of all, I would like to thank Jon`as Casanova for guiding the project on a day-to-day basis and providing everything I needed. Also, I would like to thank Prof. Jordi Cortadella for being my tutor; and my family and friends for always supporting me.  \nFinally, I would like to thank Marvell Technology, Inc. for giving me the opportunity to develop this project in a friendly and helpful environment.  \nBarcelona, 16th June 2023  \nMarc Garcia Massaneda  \nAbstract  \nThis thesis consists in developing machine learning models to predict metrics in the field of microchip design. It has been developed in collaboration with Marvell Technology, Inc., which is a company dedicated to the design and production of microchips.  \nMicrochips are designed and tested through some processes that require spending many resources. These resources need to be requested beforehand, and they can be wasted if the request doesn’t match reality. This can cost the company a lot of money and time.  \nThe main goal of this project is to solve this problem using machine learning algorithms and techniques. The creation of different models is carried out to find the most optimal solution for this problem.  \nThese machine learning models are fed with data obtained from both experimental and real projects of the company. Data comes with many problems like inconsistency and outliers. Therefore, proper preprocessing is done, as well as some transformations to get valuable information for the models.  \nThe outcome of this project is the finding of a model that uses machine learning to be able to predict these metrics successfully to strongly reduce the waste of resources.  \nKeywords  \nMicrochips design, machine learning, linear regression, decision tree, random forest, neural network, bag of words, one-hot encoding, term frequencyinverse document frequency, word2vec, mean absolute percentage error.  \nContents  \n1 Introduction 5  \n1.1 The problem ........................... 5  \n1.2 Goals and motivations ...................... 8  \n1.3 Document structure ....................... 9  \n2 State of the art 10  \n2.1 Machine learning models ..................... 10  \n2.1.1 Linear Regression ..................... 11  \n2.1.2 Decision Tree ....................... 12  \n2.1.3 Random Forest ...................... 13  \n2.1.4 Artificial Neural Network ................ 14  \n2.2 Natural language processing techniques ............ 16  \n2.2.1 Bag-of-Words ....................... 16  \n2.2.2 Term Frequency–Inverse Document Frequency .... 17  \n2.2.3 Word2Vec ......................... 18  \n3 Models 20  \n3.1 Data ................................ 20  \n3.1.1 Input metrics information ................ 20  \n3.1.2 Data extraction ...................... 22  \n3.1.3 Data cleaning ....................... 22  \n3.2 Methodology ........................... 24  \n3.2.1 Environment ....................... 24  \n3.2.2 Model Schema ...................... 25  \n3.3 Generic model .......................... 28  \n3.3.1 Vectorization ....................... 28  \n3.3.2 Model flow ........................ 30  \n3.4 Baseline metrics model ...................... 32  \n3.5 Advanced metrics model ..................... 33  \n4 Results 35  \n4.1 Generic model .......................... 36  \n4.2 Baseline metrics model ...................... 39  \n4.3","cbCailL01pgrIjo8","https://ap.wps.com/l/cbCailL01pgrIjo8","pdf",1731440,1,49,"English","en",105,"# Introduction\n## The problem\n## Goals and motivations\n## Document structure\n# State of the art\n## Machine learning models\n## Natural language processing techniques\n# Models\n## Data\n## Methodology\n## Generic model\n## Baseline metrics model\n## Advanced metrics model\n# Results\n## Generic model\n## Baseline metrics model\n## Advanced metrics model\n# Conclusions\n## Future Work","[{\"question\":\"What problem does the thesis address in ASIC design workflows?\",\"answer\":\"Jobs running on a computing grid consume limited resources, and memory requirements must be requested before execution. Memory needs are only known after running, which can cause mismatches and waste time and money.\"},{\"question\":\"How are the machine learning models trained and prepared for prediction?\",\"answer\":\"The models use data collected from experimental and real company projects. The data is processed through preprocessing and transformations to handle issues such as inconsistency and outliers before training.\"},{\"question\":\"Which machine learning and NLP approaches are explored?\",\"answer\":\"The thesis considers models such as linear regression, decision trees, random forests, and artificial neural networks. It also applies NLP techniques including bag-of-words, TF-IDF, and Word2Vec with related vectorization steps.\"}]","Machine Learning System for Resource Prediction and Tool Options Optimization for Application-Specific Integrated Circuit (ASIC) Design - Thesis Report | PDF",1785818356,123,{"code":4,"msg":31,"data":32},"ok",{"site_id":24,"language":23,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":86,"head_meta":88,"extra_data":90,"updated_unix":28},"machine-learning-system-for-resource-prediction-and-tool-options-optimization-for-application-specific-integrated-circuit-asic-design-thesis-report","",{"@graph":36,"@context":85},[37,54,68],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,48,51],{"item":41,"name":42,"@type":43,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":47},"https://docshare.wps.com/document/","Document",2,{"item":49,"name":12,"@type":43,"position":50},"https://docshare.wps.com/document/research-report/",3,{"item":52,"name":13,"@type":43,"position":53},"https://docshare.wps.com/document/machine-learning-system-for-resource-prediction-and-tool-options-optimization-for-application-specific-integrated-circuit-asic-design-thesis-report/123754/",4,{"url":52,"name":13,"@type":55,"author":56,"headline":13,"publisher":58,"fileFormat":61,"inLanguage":23,"description":14,"dateModified":62,"datePublished":62,"encodingFormat":61,"isAccessibleForFree":63,"interactionStatistic":64},"DigitalDocument",{"name":9,"@type":57},"Person",{"url":41,"name":59,"@type":60},"DocShare","Organization","application/pdf","2026-08-04",true,{"@type":65,"interactionType":66,"userInteractionCount":4},"InteractionCounter",{"@type":67},"ViewAction",{"@type":69,"mainEntity":70},"FAQPage",[71,77,81],{"name":72,"@type":73,"acceptedAnswer":74},"What problem does the thesis address in ASIC design workflows?","Question",{"text":75,"@type":76},"Jobs running on a computing grid consume limited resources, and memory requirements must be requested before execution. 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