[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-117928-en":3,"doc-seo-117928-105":30,"detail-sidebar-cat-0-en-105":82},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},117928,16904993612988,"Olivia Brown","https://ap-avatar.wpscdn.com/davatar_a8503ba1806abce46bf441b54a3ca4cd",6,"Technology","Machine Learning for Microcontroller Performance Screening - 2023","Safety-critical microcontrollers require strict quality and performance compliance, especially regarding maximum operating frequency (Fmax). Traditional speedbinning is too costly for mass production because it relies on high-end automated test equipment and extensive high-speed test patterns. Prior work shows that on-chip ring oscillators can be used with machine learning models to estimate Fmax without high-cost equipment. This research develops deployable machine learning methodologies for MCU screening, improving Fmax estimation and speed binning using a real-world microcontroller dataset.","POLITECNICO DI TORINO Repository ISTITUZIONALE  \nMachine Learning for Microcontroller Performance Screening  \nOriginal  \nMachine Learning for Microcontroller Performance Screening / Bellarmino, Nicolo'. - (2023) . (Intervento presentato al convegno 2023 IEEE European Test Symposium tenutosi a Venezia,(IT) nel 22-26 Maggio 2023) .  \nAvailability:  \nThis version is available at: 11583/2981874 since: 2023-09-10T12:14:50Z  \nPublisher: IEEE  \nPublished DOI:  \nTerms of use:  \nThis article is made available under terms and conditions as specified in the corresponding bibliographic description in the repository  \nPublisher copyright  \n(Article begins on next page)  \n17 October 2023  \nMachine Learning for Microcontroller Performance  \nScreening  \nNicol Bellarmino,  \nDip. Automatica ed Informatica  \nPolitecnico di Torino  \nTurin, Italy  \nnicolo.bellarmino@polito.it  \nAbstract—In safety-critical applications, microcontrollers must satisfy strict quality constraints and performances in terms of Fmax (the maximum operating frequency). Traditional speedbinning techniques are not feasible to be applied to mass production, due to the high cost of the needed test equipment. Literature has proven that data extracted from on-chip ring oscillators (ROs) can model the Fmax of integrated circuits by means of machine learning models able to predict the actual operating frequency of the devices. Those models, once trained, can be easily applied to the ROs data coming from every produced device with low effort and no need for high-cost equipment. This research aims to develop machine learning methodologies to be deployed in the MCU screening process, allowing for amore efficient and accurate Fmax estimation, as well as improved speed binning. The effectiveness of this approach has been demonstrated on a real-world dataset of microcontroller data.  \nIndex Terms—Fmax, Speed Monitors, Ring Oscillators, Speed Binning, Machine Learning, Device Testing, Manufacturing, Semi-Supervised Learning, Deep Learning  \nI. INTRODUCTION  \nAutomotive and aerospace industries place a strong emphasis on the reliability of electronic devices, particularly in microcontrollers (MCUs) used in safety-critical components. To ensure that these devices perform as expected, MCU performance screening is used to identify any underperforming devices that do not meet the specifications outlined in their datasheets, specifically in terms of maximum operating frequency (Fmax ) . To determine the Fmax of a device, it is tested under various worst-case conditions. Process variation during manufacturing impacts several parameters of integrated circuits, thus the performance of chips may vary across the production. Chips thus can be placed into different speed bins, depending on the performance (and chips with higher performance lead to more profit) . To maximize profits, it is important to accurately and efficiently test the chips to place them in the correct bin, by performing tests at Fmax speed, which can be divided into functional, structural (scan-based), and sensor-based tests [1] . Traditional functional methods of speed-binning involves running critical functional tests on the devices at increasing clock frequencies until a failure occurs. This permits measuring the Fmax. But this approach requires the use of high-end automated test equipment (ATE) to apply and analyze a large number of test patterns at high speed, resulting in high test overhead. Also, this approach consumes  \na large amount of memory on the tester and requires the use of costly ATE that can operate at the targeted frequency [1] . As chips designs become more complex and circuits faster the costs associated with functional testers are becoming prohibitive. Both the extended test time and the high requirement of ATEs increase the cost of traditional speed binning, making it unfeasible to be applied to large mass production. An alternative approach is to use machine learning (ML) regression models trained on data th","cbCaimZDraCsMNMD","https://ap.wps.com/l/cbCaimZDraCsMNMD","pdf",142782,1,3,"English","en",105,"# Introduction\n## MCU performance screening goals\n## Traditional speedbinning limits\n## Alternate test with machine learning\n## Challenges with scarce labeled data","[{\"question\":\"What key challenge arises when training supervised machine learning models here?\",\"answer\":\"Supervised accuracy depends on labeled data quality and quantity, but obtaining Fmax labels is time-consuming and costly. This scarcity motivates approaches that optimize labeling and handle limited labels under noisy acquisition conditions.\"}]","Machine Learning for Microcontroller Performance Screening - 2023 | PDF",1785680407,8,{"code":4,"msg":31,"data":32},"ok",{"site_id":24,"language":23,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":77,"head_meta":79,"extra_data":81,"updated_unix":28},"machine-learning-for-microcontroller-performance-screening-2023","",{"@graph":36,"@context":76},[37,53,67],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,48,50],{"item":41,"name":42,"@type":43,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":47},"https://docshare.wps.com/document/","Document",2,{"item":49,"name":12,"@type":43,"position":21},"https://docshare.wps.com/document/technology/",{"item":51,"name":13,"@type":43,"position":52},"https://docshare.wps.com/document/machine-learning-for-microcontroller-performance-screening-2023/117928/",4,{"url":51,"name":13,"@type":54,"author":55,"headline":13,"publisher":57,"fileFormat":60,"inLanguage":23,"description":14,"dateModified":61,"datePublished":61,"encodingFormat":60,"isAccessibleForFree":62,"interactionStatistic":63},"DigitalDocument",{"name":9,"@type":56},"Person",{"url":41,"name":58,"@type":59},"DocShare","Organization","application/pdf","2026-08-02",true,{"@type":64,"interactionType":65,"userInteractionCount":4},"InteractionCounter",{"@type":66},"ViewAction",{"@type":68,"mainEntity":69},"FAQPage",[70],{"name":71,"@type":72,"acceptedAnswer":73},"What key challenge arises when training supervised machine learning models here?","Question",{"text":74,"@type":75},"Supervised accuracy depends on labeled data quality and quantity, but obtaining Fmax labels is time-consuming and costly. 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