[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-119347-en":3,"doc-seo-119347-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},119347,1099514067415,"Rowan","https://ap-avatar.wpscdn.com/avatar/100002539d78ffe74a7?x-image-process=image/resize,m_fixed,w_180,h_180&k=1779092875211072502",8,"Research & Report","Machine learning evaluation in the Global Event Processor FPGA for the ATLAS trigger upgrade","The Global Event Processor (GEP) FPGA is an area-constrained, performance-critical component of the LHC ATLAS trigger system. It must rapidly decide which small fraction of detected collision events are kept for further analysis and which are rejected, meeting an end-to-end latency budget of no more than 8 ms. This work presents automated methods to generate machine-learning-based algorithms for deployment within the APP framework. Using FPGA-oriented ML tool flows such as hls4ml and fwX, the study demonstrates implementations with very low latency and minimal resource usage, then evaluates their real performance when integrated into the GEP.","arXiv :2406 . 12875v1 [physics .ins-det] 7 May 2024  \nPrepared for submission to JINST  \nMachine learning evaluation in the Global Event Processor FPGA for the ATLAS trigger upgrade  \nZhixing Jiang􀀰, ∗ Ben Carlson􀀲 Allison Deiana􀀳 Jeff Eastlack􀀴 Scott Hauck􀀰 Shih-Chieh Hsu􀀱 Rohin Narayan􀀳 Santosh Parajuli 􀀳 Dennis Yin􀀰 Bowen Zuo􀀰  \n􀀰 Department of Electrical & Computer Engineering, University of Washington, 1410 NE Campus Parkway, Seattle, WA, USA  \n􀀱 Department of Physics, University of Washington, 1410 NE Campus Parkway, Seattle, WA, USA  \n􀀲 Department of Physics & Astronomy, Westmont College and University of Pittsburgh, 3941 O’Hara St, Pittsburgh, PA, USA  \n􀀳 Department of Physics, Southern Methodist University, 3225 University Blvd., Dallas, TX, USA  \n􀀴 Department of Physics & Astronomy, Michigan State University,  \n288 Farm Lane, East Lansing, MI, USA E-mail: [zhixij@uw.edu](zhixij@uw.edu)*  \nAbstract: The Global Event Processor (GEP) FPGA is an area-constrained, performance-critical element of the Large Hadron Collider’s (LHC) ATLAS experiment. It needs to very quickly determine which small fraction of detected events should be retained for further processing, and which other events will be discarded. This system involves a large number of individual processing tasks, brought together within the overall Algorithm Processing Platform (APP), to make filtering decisions at an overall latency of no more than 8ms. Currently, such filtering tasks are hand-coded implementations of standard deterministic signal processing tasks.  \nIn this paper we present methods to automatically create machine learning based algorithms for use within the APP framework, and demonstrate several successful such deployments. We leverage existing machine learning to FPGA flows such as hls4ml and fwX to significantly reduce the complexity of algorithm design. These have resulted in implementations of various machine learning algorithms with latencies of 1.2􀁠􀁂 and less than 5% resource utilization on an Xilinx XCVU9P FPGA. Finally, we implement these algorithms into the GEP system and present their actual performance.  \nOur work shows the potential of using machine learning in the GEP for high-energy physics applications. This can significantly improve the performance of the trigger system and enable the ATLAS experiment to collect more data and make more discoveries. The architecture and approach presented in this paper can also be applied to other applications that require real-time processing of large volumes of data.  \nKeywords: Accelerator applications; Hardware and accelerator control systems; Trigger detectors; Data processing methods  \nContents  \n1 Introduction 1  \n2 Infrastructure and Methods 2  \n2.1 Integration of the Algorithm 2  \n2.2 Data Transmission and Synchronization 4  \n2.3 hls4ml 5  \n2.4 fwX 6  \n3 Experimental Result 7  \n3.1 Deep Neural Network for B-tagging 7  \n3.2 VBF Classification in BDTs 8  \n3.3 Missing Transverse Momentum Regression BDT 9  \n3.4 Quark-Gluon Jet Tagging Algorithm 9  \n4 Conclusion 10  \n1 Introduction  \nThe ATLAS experiment at the LHC [1] at CERN is undergoing continuous upgrades as part of the High-Luminosity LHC Upgrade [2] due to the need to handle an increased data output rate andrefine data capture accuracy for the upcoming High-Luminosity LHC upgrade [3] . The upgrades include a new decision-making module, the Global Trigger subsystem, in the L0 Trigger [4] . The L0 trigger is the first-level, hardware-based decision system that selects relevant collision events for further analysis, which will require new and improved hardware and algorithms to increase its performance.  \nThe upcoming Global Trigger subsystem is designed to run advanced algorithms, similar to those typically used for offline data analysis, on detailed data collected from various sub-detectors and processing units in real time. This approach will enhance the quality of detected events and observables, serving as inputs for the advanced decis","cbCaibCkcDTTFj3C","https://ap.wps.com/l/cbCaibCkcDTTFj3C","pdf",580343,1,14,"English","en",105,"# Introduction\n# Infrastructure and Methods\n## Integration of the Algorithm\n## Data Transmission and Synchronization\n## hls4ml\n## fwX\n# Experimental Result\n## Deep Neural Network for B-tagging\n## VBF Classification in BDTs\n## Missing Transverse Momentum Regression BDT\n## Quark-Gluon Jet Tagging Algorithm\n# Conclusion","[{\"question\":\"What role does the Global Event Processor (GEP) FPGA play in the ATLAS trigger upgrade?\",\"answer\":\"The GEP FPGA performs performance-critical filtering decisions in real time, determining which detected collision events are retained for further processing and which are discarded within a strict latency budget.\"},{\"question\":\"How does the paper create machine-learning-based algorithms for deployment on the FPGA?\",\"answer\":\"It uses automated generation approaches within the APP framework and leverages existing ML-to-FPGA flows such as hls4ml and fwX to reduce algorithm design complexity and enable FPGA implementations.\"},{\"question\":\"What results are reported for the deployed machine-learning algorithms on the FPGA?\",\"answer\":\"The study reports FPGA implementations achieving low latency and low resource utilization, and then evaluates their actual performance after integrating the algorithms into the GEP system.\"}]","Machine learning evaluation in the Global Event Processor FPGA for the ATLAS trigger upgrade | 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role does the Global Event Processor (GEP) FPGA play in the ATLAS trigger upgrade?","Question",{"text":75,"@type":76},"The GEP FPGA performs performance-critical filtering decisions in real time, determining which detected collision events are retained for further processing and which are discarded within a strict latency budget.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"How does the paper create machine-learning-based algorithms for deployment on the FPGA?",{"text":80,"@type":76},"It uses automated generation approaches within the APP framework and leverages existing ML-to-FPGA flows such as hls4ml and fwX to reduce algorithm design complexity and enable FPGA implementations.",{"name":82,"@type":73,"acceptedAnswer":83},"What results are reported for the deployed machine-learning algorithms on the FPGA?",{"text":84,"@type":76},"The study reports FPGA implementations achieving low latency and low resource utilization, and then evaluates their actual performance after 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