[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-118405-en":3,"doc-seo-118405-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},118405,1099514067438,"River Wang","https://ap-avatar.wpscdn.com/avatar/100002539ee87300030?x-image-process=image/resize,m_fixed,w_180,h_180&k=1780474512215547542",8,"Research & Report","MACHINE LEARNING BASED PREDICTION IN FPGA CAD - Dissertation","Machine learning-based prediction methods are integrated with FPGA-oriented EDA flows to reduce costly iterations in physical design. The dissertation addresses five significant FPGA automation challenges including post-route congestion estimation, training-data generation from a single HLS code, and robust prediction of post-route QoR from behavioral descriptions without re-synthesizing. It further introduces generalized resource and performance estimation for CNN architectures and a fast design space explorer combining metaheuristics with machine learning to optimize area and latency.","MACHINE LEARNING BASED PREDICTION IN FPGA CAD  \nby  \nPingakshya Goswami  \nAPPROVED BY SUPERVISORY COMMITTEE:  \n\n| Dinesh Bhatia, Chair |\n| --- |\n| Benjamin Carrion Schaefer |\n| Poras T. Balsara |\n\nMehrdad Nourani  \nCopyright © 2022 Pingakshya Goswami All rights reserved  \nThis dissertation is  \ndedicated to my parents,  \nfor their constant encouragement & inspiration.  \nMACHINE LEARNING BASED PREDICTION IN FPGA CAD  \nby  \nPINGAKSHYA GOSWAMI, BS, MS  \nDISSERTATION  \nPresented to the Faculty of The University of Texas at Dallas in Partial Ful􀀌llment of the Requirements  \nfor the Degree of  \nDOCTOR OF PHILOSOPHY IN  \nELECTRICAL ENGINEERING  \nTHE UNIVERSITY OF TEXAS AT DALLAS  \nMay 2022  \nACKNOWLEDGMENTS  \nFirst and foremost, would like to thank Dr. Dinesh K. Bhatia for giving me the opportunity to pursue my PhD in the IDEA lab. His enthusiasm in research and immense knowledge inspired me, and his guidance has always been helpful throughout my PhD study. I would also like to thank Dr. Benjamin Carrion Schaefer for reviewing some of my papers and giving valuable feedback about them. I am fortunate enough to discuss my ideas about HLSand DSE with him, which helped me a lot. My heartfelt thanks to my other committee members Dr. Mehrdad Nourani and Dr. Poras Balsara for their insightful comments and encouragement in the completion of my dissertation.  \nI would like to thank my IDEA Lab friends, Masoud, Sneha, Hesam and Mark, for the good times we had both inside and outside the lab. Masoud was really helpful in discussing various technical details related to CNNs, DSE and HLS. I would take this opportunity to thank IDEA Lab alumni, Girish, Mohid and Devendra, for their company to discuss FPGA related stu􀀋s and all the fun we had together.  \nI would like to thank my Dallas friends, Jugal, Jyotirmoy, Mrinmoy, Devang and Akshay, for making my PhD a memorable journey. They wholeheartedly encouraged me and provided immense support during the COVID-19 pandemic period.  \nFinally, I would like to express my gratitude to my parents for all the encouragement and inspiration they gave through Phone and Skype during my four and half years at UT Dallas. Last but not least, I would like to deeply thank my wife Poulami, for being loving, caring, and supportive in the past four years.  \nFebruary 2022  \nMACHINE LEARNING BASED PREDICTION IN FPGA CAD  \nPingakshya Goswami, PhD  \nThe University of Texas at Dallas, 2022  \nSupervising Professor: Dinesh Bhatia, Chair  \nTechnological advances have allowed the continuous improvement of modern electronic systems. Enabled by the scaling of technology nodes, current integrated circuits are becoming increasingly complex. These intricate designs require EDA tools to ensure the rapid creation of complex new-generation architectures. Traditionally, a hardware IC design engineer designs the chips with the help of RTL language like Verilog, VHDL, or System Verilog. However, creating chips using RTL descriptions becomes challenging for the new generation of complex architectures addressing applications like deep learning and computer vision. Asa result, designers nowadays use high-level languages like C/C++ or System C to design the chips. The design 􀀍ows consist of multiple stages, from C-synthesis (converting C/C++ code to RTL code) to place and route. Each step is highly time-consuming, and the performance of each stage is very much dependent on the characteristics of the previous stage.  \nThe use of machine learning (ML) to help speed up electronic system design is becoming prevalent across the industry. This dissertation is a fusion of ML and EDA tools. We have solved multiple electronic design automation (EDA) problems for 􀀌eld-programmable gate arrays (FPGAs) technology. This dissertation applied ML to solve 􀀌ve signi􀀌cant FPGA physical design automation problems. Design closure in general VLSI physical design 􀀍ows, and FPGA physical design 􀀍ows are important and time-consuming problems. Routing can consume as mu","cbCaiv2ZqFvkue6L","https://ap.wps.com/l/cbCaiv2ZqFvkue6L","pdf",4740515,1,183,"English","en",105,"# Acknowledgments\n# Abstract\n# Introduction\n## EDA challenges and motivation\n## Machine learning integration for FPGA design","[{\"question\":\"What is the main focus of this dissertation?\",\"answer\":\"The work combines machine learning with FPGA CAD and EDA flows to predict and estimate key physical design outcomes, reducing time-consuming implementation cycles.\"},{\"question\":\"Which problems in FPGA design are addressed?\",\"answer\":\"It addresses five FPGA physical design automation problems, including post-route congestion estimation, training-set generation from HLS, post-route QoR prediction, CNN resource/performance estimation, and fast design space exploration.\"},{\"question\":\"How does the dissertation handle limited training data in EDA workflows?\",\"answer\":\"It emphasizes the quality and quantity of training data and proposes a methodology to create large training design sets from a single HLS code to mitigate data scarcity.\"}]","MACHINE LEARNING BASED PREDICTION IN FPGA CAD - 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