[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-124354-en":3,"doc-seo-124354-105":29,"detail-sidebar-cat-0-en-105":90},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":11,"language":21,"language_code":22,"site_id":23,"html_lang":22,"table_of_contents":24,"faqs":25,"seo_title":26,"seo_description":14,"update_tm":27,"read_time":28},124354,962075114101,"Seraphina","https://ap-avatar.wpscdn.com/avatar/e000253a75eb197efd?x-image-process=image/resize,m_fixed,w_180,h_180&k=1780044092746381165",8,"Research & Report","Machine Learning-based feasibility estimation of digital blocks in BCD technology - Conference paper","Analog-on-Top mixed-signal integrated circuit design relies heavily on manual effort, especially when reserving silicon area for digital blocks. Area properties such as size and shape directly affect whether the intended digital logic can be implemented with the required functionality. The work proposes a machine learning–based evaluation methodology that predicts digital implementation feasibility using high-level features. The goal is to eliminate time-consuming Place-and-Route trials, providing faster feedback between Digital and Analog back-end designers during top-level placement.","POLITECNICO DI TORINO  \nRepository ISTITUZIONALE  \nMachine Learning-based feasibility estimation of digital blocks in BCD technology  \nOriginal  \nMachine Learning-based feasibility estimation of digital blocks in BCD technology / Daghero, Francesco; Faraone, Gabriele; Grosso, Michelangelo; Pagliari, Daniele Jahier; Di Carolo, Nicola; Franchino, Giovanna Antonella; Licastro, Dario; Serianni, Eugenio. -ELETTRONICO. - (2024), pp. 1-6. (Intervento presentato al convegno 2024 IEEE International Conference on Design, Test and Technology of Integrated Systems, DTTIS 2024 tenutosi a Aix-EnProvence, France nel 14-16 October 2024) [10 . 1109/dttis62212 .2024. 10780062] .  \nAvailability:  \nThis version is available at: 11583/2999020 since: 2025-04-10T10:06:35Z  \nPublisher:  \nInstitute of Electrical and Electronics Engineers Inc.  \nPublished  \nDOI:10.1109/dttis62212.2024.10780062  \nTerms of use:  \nThis article is made available under terms and conditions as specified in the corresponding bibliographic description in the repository  \nPublisher copyright  \nIEEE postprint/Author's Accepted Manuscript  \n©2024 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collecting works, for resale or lists, or reuse of any copyrighted component of this work in other works.  \n(Article begins on next page)  \n04 October 2025  \nMachine Learning-based feasibility estimation of digital blocks in BCD technology  \nFrancesco Daghero Department of Control and Computer Engineering Politecnico di Torino 10129, Turin, Italy francesco.daghero@polito.it  \nNicola Di Carolo Analog, Power & Discrete  \nMEMS and Sensor R&D group STMicroelectronics 20864, Agrate Brianza, Italy [nicola.dicarolo@st.com](nicola.dicarolo@st.com)  \nGabriele Faraone Analog, Power & Discrete  \nMEMS and Sensor R&D group STMicroelectronics 20864, Agrate Brianza, Italy [gabriele.faraone@st.com](gabriele.faraone@st.com)  \nGiovanna Antonella Franchino Analog, Power & Discrete  \nMEMS and Sensor R&D group STMicroelectronics 20864, Agrate Brianza, Italy [giovanna.franchino@st.com](giovanna.franchino@st.com)  \nMichelangelo Grosso Analog, Power & Discrete MEMS and Sensor R&D group STMicroelectronics 10129, Turin, Italy [michelangelo.grosso@st.com](michelangelo.grosso@st.com)  \nDario Licastro  \nAnalog, Power & Discrete MEMS and Sensor R&D group STMicroelectronics 10129, Turin, Italy [dario.licastro@st.com](dario.licastro@st.com)  \nDaniele Jahier Pagliari Department of Control and Computer Engineering Politecnico di Torino 10129, Turin, Italy daniele.jahier@polito.it  \nEugenio Serianni Analog, Power & Discrete MEMS and Sensor R&D group STMicroelectronics 20864, Agrate Brianza, Italy [eugenio.serianni@st.com](eugenio.serianni@st.com)  \nAbstract—Analog-on-Top Mixed Signal (AMS) Integrated Circuit (IC) design is a time-consuming process predominantly carried out by hand. Within this flow, usually, some area is reserved by the top-level integrator for the placement of digital blocks. Specific features of the area, such as size and shape, have a relevant impact on the possibility of implementing the digital logic with the required functionality. We present a Machine Learning (ML)-based evaluation methodology for predicting the feasibility of digital implementation using a set of high-level features. This approach aims to avoid time-consuming Place-and-Route trials, enabling rapid feedback between Digital and Analog Back-End designers during top-level placement.  \nKeywords—EDA, layout, Place and Route, machine learning, artificial intelligence, analog-mixed-signal, integrated circuits  \nI. INTRODUCTION  \nIn the field of electronic Integrated Circuit (IC) design, the Physical Design (PD) of Analog and mixed-signal (AMS) ICs is often based on the “Analog-on-Top” approach. This approach involves instantiating all digital subsyste","cbCaikb67eoMfM2o","https://ap.wps.com/l/cbCaikb67eoMfM2o","pdf",578054,1,"English","en",105,"# Abstract\n## Introduction\n## ML-based evaluation methodology\n## Benefits for top-level placement","[{\"question\":\"Why is analog-on-Top mixed-signal IC design time-consuming in this workflow?\",\"answer\":\"Because the analog-on-top flow reserves area for digital blocks and the feasibility depends on area characteristics, which are typically handled with manual, time-consuming placement and exploration.\"},{\"question\":\"What does the proposed approach predict?\",\"answer\":\"It predicts the feasibility of digital implementation using a set of high-level features, aiming to estimate whether digital logic can be realized with required functionality.\"},{\"question\":\"How does the methodology improve the design process?\",\"answer\":\"By reducing the need for full Place-and-Route trials, it enables rapid feedback between digital and analog back-end designers during top-level placement.\"}]","Machine Learning-based feasibility estimation of digital blocks in BCD technology - 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