[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-151939-en":3,"doc-seo-151939-105":30,"detail-sidebar-cat-0-en-105":92},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},151939,687197100911,"Himbo","https://ap-avatar.wpscdn.com/avatar/a000239b6f1da00475?x-image-process=image/resize,m_fixed,w_180,h_180&k=1785132997149421697",8,"Research & Report","Loop Rerolling for Hardware Decompilation - Research Paper","Hardware decompilation reconstructs higher-level HDL abstractions from a low-level netlist, enabling recovered code to be used as a semantically equivalent program. This paper targets hardware loop rerolling, a technique that applies clone detection and program synthesis to find repeated logic patterns in netlists and reroll them into syntactic loops in the recovered HDL. Evaluation on PyRTL and SystemVerilog benchmarks rerolls loops in 52 of 53 netlists and demonstrates benefits including HDL transpilation, 6x mean simulation speedups, and 39% average artifact compaction.","Loop Rerolling for Hardware Decompilation  \nZACHARY D. SISCO, University of California, Santa Barbara, USA JONATHAN BALKIND, University of California, Santa Barbara, USA TIMOTHY SHERWOOD, University of California, Santa Barbara, USA BEN HARDEKOPF, University of California, Santa Barbara, USA  \nWe introduce the new problem of hardware decompilation. Analogous to software decompilation, hardware decompilation is about analyzing a low-level artifact—in this case a netlist, i.e., a graph of wires and logical gates representing a digital circuit—in order to recover higher-level programming abstractions, and using those abstractions to generate code written in a hardware description language (HDL) . The overall problem of hardware decompilation requires a number of pieces. In this paper we focus on one specific piece of the puzzle: a technique we call hardware loop rerolling. Hardware loop rerolling leverages clone detection and program synthesis techniques to identify repeated logic in netlists (such as would be synthesized from loops in the original HDL code) and reroll them into syntactic loops in the recovered HDL code. We evaluate hardware loop rerolling for hardware decompilation over a set of hardware design benchmarks written in the PyRTL HDL and industry standard SystemVerilog. Our implementation identifies and rerolls loops in 52 out of 53 of the netlists in our benchmark suite, and we show three examples of how hardware decompilation can provide concrete benefits: transpilation between HDLs, faster simulation times over netlists (with mean speedup of 6x), and artifact compaction (39% smaller on average) .  \nCCS Concepts: • Hardware → Hardware description languages and compilation; Software tools forEDA. Additional Key Words and Phrases: hardware decompilation, program synthesis, loop rerolling  \nACM Reference Format:  \nZachary D. Sisco, Jonathan Balkind, Timothy Sherwood, and Ben Hardekopf. 2023. Loop Rerolling for Hardware Decompilation. Proc. ACM Program. Lang. 7, PLDI, Article 123 (June 2023), 23 pages. [https://doi.org/10.1145/](https://doi.org/10.1145/)[ ](https://doi.org/10.1145/)3591237  \n1 INTRODUCTION  \nHardware description languages (HDLs) are a key tool in the hardware development process. HDLs provide high-level programmatic abstractions for designing, simulating, verifying, and synthesizing hardware. Synthesizing HDL code generates a layout of wires and logical gates represented as a graph called a netlist. After synthesis, the resulting netlist loses many of the high-level details from the HDL code such as loops, functions, and modules. The netlist is also considerably larger than the HDL code that generates it.  \nThis paper introduces a new research problem: hardware decompilation, that is, transforming a netlist into a semantically identical HDL program at a higher level of abstraction. The idea is analogous to software decompilation, wherein an executable binary is lifted back to source code ina high-level programming language, but targets netlists (rather than executables) and HDLs (rather than general-purpose programming languages) .  \nAuthors’ addresses: Zachary D. Sisco, University of California, Santa Barbara, USA, [zsisco@ucsb.edu](zsisco@ucsb.edu); Jonathan Balkind, University of California, Santa Barbara, USA, [jbalkind@ucsb.edu](jbalkind@ucsb.edu); Timothy Sherwood, University of California, Santa  \nBarbara, USA, [sherwood@cs.ucsb.edu](sherwood@cs.ucsb.edu); Ben Hardekopf, University of California, Santa Barbara, USA, [benh@cs.ucsb.edu](benh@cs.ucsb.edu).  \nPermission to make digital or hard copies of part or all ofthis work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for third-party components of this work must be honored. For all other uses, contact the owner/author(s) .  \n© 2023 Copyright held by the owner/author(s) . ","cbCairDriQY4tF6X","https://ap.wps.com/l/cbCairDriQY4tF6X","pdf",1303270,1,23,"English","en",105,"# Introduction\n## Motivating Hardware Decompilation\n# Hardware Loop Rerolling\n## Loop Identification and Rerolling\n# Evaluation and Results\n## Benchmark Coverage\n## Case Studies and Benefits","[{\"question\":\"什么是硬件反编译（hardware decompilation）？\",\"answer\":\"硬件反编译是把一个语义等价的“高层”HDL程序从低层网表（netlist）中恢复出来。网表由连线与逻辑门构成，通常在综合后会丢失HDL中的循环、函数和模块等高层结构。\"},{\"question\":\"硬件循环再展开（hardware loop rerolling）的核心做法是什么？\",\"answer\":\"该方法利用克隆检测与程序合成，识别网表中重复的逻辑模式，并把这些模式“再展开”为恢复HDL代码中的语法循环。\"},{\"question\":\"论文的实验评估结果有哪些关键结论？\",\"answer\":\"在52/53个基准网表上成功进行循环再展开，并展示三项应用收益：HDL之间的自动转译、基于网表的仿真速度提升（平均6倍），以及产物体积的压缩（平均减少39%）。\"}]","Loop Rerolling for Hardware Decompilation - Research Paper | PDF",1787853224,58,{"code":4,"msg":31,"data":32},"ok",{"site_id":24,"language":23,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":87,"head_meta":89,"extra_data":91,"updated_unix":28},"loop-rerolling-for-hardware-decompilation-research-paper","",{"@graph":36,"@context":86},[37,54,69],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,48,51],{"item":41,"name":42,"@type":43,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":47},"https://docshare.wps.com/document/","Document",2,{"item":49,"name":12,"@type":43,"position":50},"https://docshare.wps.com/document/research-report/",3,{"item":52,"name":13,"@type":43,"position":53},"https://docshare.wps.com/document/loop-rerolling-for-hardware-decompilation-research-paper/151939/",4,{"url":52,"name":13,"@type":55,"author":56,"headline":13,"publisher":58,"fileFormat":61,"inLanguage":23,"description":14,"dateModified":62,"datePublished":63,"encodingFormat":61,"isAccessibleForFree":64,"interactionStatistic":65},"DigitalDocument",{"name":9,"@type":57},"Person",{"url":41,"name":59,"@type":60},"DocShare","Organization","application/pdf","2026-09-04","2026-08-27",true,{"@type":66,"interactionType":67,"userInteractionCount":20},"InteractionCounter",{"@type":68},"ViewAction",{"@type":70,"mainEntity":71},"FAQPage",[72,78,82],{"name":73,"@type":74,"acceptedAnswer":75},"什么是硬件反编译（hardware decompilation）？","Question",{"text":76,"@type":77},"硬件反编译是把一个语义等价的“高层”HDL程序从低层网表（netlist）中恢复出来。网表由连线与逻辑门构成，通常在综合后会丢失HDL中的循环、函数和模块等高层结构。","Answer",{"name":79,"@type":74,"acceptedAnswer":80},"硬件循环再展开（hardware loop rerolling）的核心做法是什么？",{"text":81,"@type":77},"该方法利用克隆检测与程序合成，识别网表中重复的逻辑模式，并把这些模式“再展开”为恢复HDL代码中的语法循环。",{"name":83,"@type":74,"acceptedAnswer":84},"论文的实验评估结果有哪些关键结论？",{"text":85,"@type":77},"在52/53个基准网表上成功进行循环再展开，并展示三项应用收益：HDL之间的自动转译、基于网表的仿真速度提升（平均6倍），以及产物体积的压缩（平均减少39%）。","https://schema.org",{"og:url":52,"og:type":88,"og:title":13,"og:site_name":59,"og:description":14},"article",{"robots":90,"canonical":52},"index,follow",{"doc_id":7,"site_id":24},{"code":4,"msg":5,"data":93},[94,98,102,106,111,116,121,124,129,132,136],{"id":20,"doc_module":4,"doc_module_name":46,"category_name":95,"show_sort_weight":96,"slug":97},"Story & Novel",90,"story-novel",{"id":47,"doc_module":4,"doc_module_name":46,"category_name":99,"show_sort_weight":100,"slug":101},"Literature",80,"literature",{"id":53,"doc_module":4,"doc_module_name":46,"category_name":103,"show_sort_weight":104,"slug":105},"Exam",70,"exam",{"id":107,"doc_module":4,"doc_module_name":46,"category_name":108,"show_sort_weight":109,"slug":110},5,"Comic",60,"comic",{"id":112,"doc_module":4,"doc_module_name":46,"category_name":113,"show_sort_weight":114,"slug":115},6,"Technology",50,"technology",{"id":117,"doc_module":4,"doc_module_name":46,"category_name":118,"show_sort_weight":119,"slug":120},7,"Healthcare",40,"healthcare",{"id":11,"doc_module":4,"doc_module_name":46,"category_name":12,"show_sort_weight":122,"slug":123},30,"research-report",{"id":125,"doc_module":4,"doc_module_name":46,"category_name":126,"show_sort_weight":127,"slug":128},9,"Religion & Spirituality",20,"religion-spirituality",{"id":127,"doc_module":4,"doc_module_name":46,"category_name":130,"show_sort_weight":127,"slug":131},"World Cup","world-cup",{"id":133,"doc_module":4,"doc_module_name":46,"category_name":134,"show_sort_weight":133,"slug":135},10,"Lifestyle","lifestyle",{"id":137,"doc_module":4,"doc_module_name":46,"category_name":138,"show_sort_weight":107,"slug":139},19,"General","general"]