[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-657679-105":59,"doc-detail-657679-en":130},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":123,"head_meta":125,"extra_data":127,"updated_unix":129},105,"en","logic-diagrams-logic-diagram-basics","LOGIC DIAGRAMS - Logic Diagram Basics","","Logic diagrams define standardized binary logic symbols and their operating rules for process operations. The content specifies how inputs and memory elements interact, including set/reset behavior using SR flip-flop notation. It also describes AND/OR/NOT basic logic outputs and covers timing elements such as delayed initiation, delayed termination, and pulse output with duration t. Additional options address input override and loss-of-power-supply behavior. Symbology is referenced to ANSI/SA-S5.2.",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":30,"@type":76,"position":81},"https://docshare.wps.com/document/technology/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/logic-diagrams-logic-diagram-basics/657679/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/logic-diagrams-logic-diagram-basics/657679.png","ImageObject",300,407,{"name":92,"@type":93},"Aria","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-30","2026-10-26",true,{"@type":102,"interactionType":103,"userInteractionCount":8},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"How does the flip-flop memory behave for set and reset inputs?","Question",{"text":112,"@type":113},"S represents set memory and R represents reset memory. Output C exists as soon as input A exists and remains until memory is reset by input B existing.","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"What determines whether an AND basic logic output exists?",{"text":117,"@type":113},"Logic output D exists if and only if all logic inputs A, B, and C exist.",{"name":119,"@type":110,"acceptedAnswer":120},"What timing behaviors are defined by the time element basics?",{"text":121,"@type":113},"The diagrams define delayed initiation, delayed termination, and pulse output. Each specifies when output B exists relative to when input A persists or terminates for a time t.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},657679,1792986195,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":133,"doc_module":4,"category_id":29,"category_name":30,"doc_title":65,"doc_description":67,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":8,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":8,"language":139,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":140,"faqs":141,"seo_title":142,"seo_description":67,"update_tm":129,"read_time":81},2336464648322,"https://ap-avatar.wpscdn.com/avatar/2200025388227c56fec?_k=1778556882303663488","| REVISION INDEX   |  |  |  |  |  |  |  |  |  | 1.  \u003Cbr>INPUT   | Alternatively:  \u003Cbr>Statement  \u003Cbr>of Input  \u003Cbr>lnitiating instrument or  \u003Cbr>device number,if known   | An input to the logic sequence.   |  | 9.  \u003Cbr>MEMORY  \u003Cbr>(FLIP-FLOP)  \u003Cbr>BASIC   |  | a)  \u003Cbr>C  \u003Cbr>SR  \u003Cbr>D*  \u003Cbr>B  \u003Cbr>*Output D shall not be shown  \u003Cbr>if it is not used.   | S represents set memory and  \u003Cbr>R represents reset memory.  \u003Cbr>Logic output C exists as soon as logic  \u003Cbr>input A exists.C continues to exist,regardless  \u003Cbr>of the subsequent state of A,until the memory  \u003Cbr>is reset,i.e.,terminated by logic input B existing.  \u003Cbr>C remains terminated regardless of the subsequent  \u003Cbr>state of B,until A couses the memory to be set.  \u003Cbr>Logic output D,if used,exists when C does not  \u003Cbr>exist,and D does not exist when C exists.   |  |\n| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |\n| PAGE  \u003Cbr>No.   | DESCRIPTION   | REVISION   |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |\n|  |  | 0   |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |\n| 2  \u003Cbr>3  \u003Cbr>4.1  \u003Cbr>4.2  \u003Cbr>4.3  \u003Cbr>4.4  \u003Cbr>4.5  \u003Cbr>4.6  \u003Cbr>4.7  \u003Cbr>4.8  \u003Cbr>5  \u003Cbr>6  \u003Cbr>7.1  \u003Cbr>7.2  \u003Cbr>7.3  \u003Cbr>7.4  \u003Cbr>7.5  \u003Cbr>7.6  \u003Cbr>8  \u003Cbr>9   | GRS IN AUTO  \u003Cbr>STREAM SELECTION  \u003Cbr>ESD VALVES  \u003Cbr>FILT.SKID STREAM 1 NLET VALVE  \u003Cbr>FILT.SKID STREAM 2 INLET VALVE  \u003Cbr>REGUL.SKID STREAM 1 NLET VALVE  \u003Cbr>REGUL.SKID STREAM 10UTLET VALVE  \u003Cbr>REGUL.SKID COMPR.STREAM INLET VALVE  \u003Cbr>REGUL.SKID COMPR.STREAM OUTLET VALVE  \u003Cbr>REGUL.SKID STREAM 2 INLET VALVE  \u003Cbr>REGUL.SKID STREAM 2 OUTLET VALVE  \u003Cbr>COMPRESSOR  \u003Cbr>CCPP SIGNALS  \u003Cbr>FLT.SKID STREAM 10UTLET VALVE  \u003Cbr>FLT.SKID STREAM 2 OUTLET VALVE  \u003Cbr>METERING SKID INLET VALVE  \u003Cbr>METERING SKID OUTLET VALVE  \u003Cbr>METERING SKID BY-PASS VALVE  \u003Cbr>COMPR.DISCHARGE VALVE  \u003Cbr>HOT WATER CIRCUT  \u003Cbr>PANEL NDICATION LAMPS   | X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X   | X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X   | X  \u003Cbr>X  \u003Cbr>X  \u003Cbr>X   | X   |  |  |  |  |  |  |  |  |  |  |  |  |  |\n|  |  |  |  |  |  |  |  |  |  | 2.  \u003Cbr>OUTPUT   | Alternatively:  \u003Cbr>Statement  \u003Cbr>of Output  \u003Cbr>Operated instrument or  \u003Cbr>device number,if known   | An output to the logic sequence.   |  |  |  |  |  |  |\n|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | Input-0verride Option  \u003Cbr>If inputs A and B exist simultaneously,and if it is  \u003Cbr>desired to have A overrde B,then S should be  \u003Cbr>encircled,i.e.,⑤;if B is to overide A,then R should  \u003Cbr>be encircled,i.e.,R.  \u003Cbr>Loss-Of-Power-Supply Option  \u003Cbr>The unmodified letter S denotes that no consideration  \u003Cbr>has been given to the action of the memory on loss  \u003Cbr>of the logic power supply.See paragraphs  \u003Cbr>6.b and c,bellow.   |  |\n|  |  |  |  |  |  |  |  |  |  | 3.  \u003Cbr>AND  \u003Cbr>BASIC   | A  \u003Cbr>D   | Logic output D exists if and only if all  \u003Cbr>logic inputs A,B,and C exist.   |  |  |  |  |  |  |\n|  |  |  |  |  |  |  |  |  |  | 4.  \u003Cbr>OR  \u003Cbr>BASIC   | D  \u003Cbr>OR  \u003Cbr>CH   | Logic output D exists if and only if one  \u003Cbr>or more of logic inputs A,B,and C exist.   |  |  |  |  |  |  |\n|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | b),  \u003Cbr>A  \u003Cbr>5R  \u003Cbr>CD  \u003Cbr>B   | Similar to definition of symbol (a)except that the  \u003Cbr>memory shall be lost in the event of loss of the  \u003Cbr>logic power supply.   |  |\n|  |  |  |  |  |  |  |  |  |  | 5.  \u003Cbr>NOT  \u003Cbr>BASIC   | AH  \u003Cbr>The NOT symbol may  \u003Cbr>be drawn tangent to an  \u003Cbr>odjacent logic symbol.   | Logic output B exists if and only if  \u003Cbr>logic input A does not exist.   |  |  |  |  |  |  |\n|  |  |  |  |  |  |  |  |  |  |  |  |  |  |  |  | c)  \u003Cbr>MS  \u003Cbr>A1  \u003Cbr>C  \u003Cbr>B  \u003Cbr>D  \u003Cbr>R   | Similar to definition of symbol(a)except that the  \u003Cbr>memory shall be maintained in the event of loss  \u003Cbr>of the logic power supply.   |  |\n|  |  |  |  |  |  |  |  |  |  | 6.  \u003Cbr>TIME  \u003Cbr>ELEMENT  \u003Cbr>BASIC   | B  \u003Cbr>AH  \u003Cbr>P  \u003Cbr>(Delay Initiotion of outp","cbCaifiQFQa63aNo","https://ap.wps.com/l/cbCaifiQFQa63aNo","pdf",141689,"English","# Logic Diagram Basics\n## Input and Output Definitions\n## Memory (Flip-Flop) Basic and Options\n## AND Basic\n## OR Basic\n## NOT Basic\n## Time Element Basics","[{\"question\":\"How does the flip-flop memory behave for set and reset inputs?\",\"answer\":\"S represents set memory and R represents reset memory. Output C exists as soon as input A exists and remains until memory is reset by input B existing.\"},{\"question\":\"What determines whether an AND basic logic output exists?\",\"answer\":\"Logic output D exists if and only if all logic inputs A, B, and C exist.\"},{\"question\":\"What timing behaviors are defined by the time element basics?\",\"answer\":\"The diagrams define delayed initiation, delayed termination, and pulse output. Each specifies when output B exists relative to when input A persists or terminates for a time t.\"}]","LOGIC DIAGRAMS - Logic Diagram Basics | PDF"]