[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-84993-en":3,"doc-seo-84993-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":21,"is_downloadable":21,"audit_status":21,"page_count":22,"language":23,"language_code":24,"site_id":25,"html_lang":24,"table_of_contents":26,"faqs":27,"seo_title":13,"seo_description":14,"update_tm":28,"read_time":29},84993,13056703019404,"Miles","https://ap-avatar.wpscdn.com/davatar_29158cc5080c5b710cf443261637dec0",8,"Research & Report","LLM Assisted Verification Assertion Generation: Challenges and Future Directions","Assertion-based verification (ABV) is essential in the design verification (DV) workflow, yet it is highly manual because verification engineers must derive assertions from specifications, making it time-consuming and error-prone. With recent large language model (LLM) advances, researchers increasingly explore using LLMs to assist ABV, especially generating SystemVerilog Assertions (SVAs) from design specifications. This paper reviews recent methods and studies how to make LLM-based assertion generation systematic and quality-aware, offering challenge takeaways, guidelines, and future directions for high-quality assertions.","LLM Assisted Verification Assertion Generation: Challenges and Future Directions  \nBhabesh Mali, Chandan Karfa  \nIndian Institute of Technology Guwahati, India  \n{m.bhabesh, [ckarfa](ckarfa}@iitg.ac.in)[}](ckarfa}@iitg.ac.in)[@iitg.ac.in](ckarfa}@iitg.ac.in)  \narXiv :2607 .07444v 1 [ cs .ET] 8 Jul 2026  \nAbstract—Assertion-based Verification (ABV) plays a critical role in the Design Verification (DV) process. However, ABV requires substantial manual effort in generating assertion from specification by verification engineers, making it a timeconsuming stage in the chip design flow. With the recent development of Large Language Models (LLMs), researchers have started exploring their use as an assistance in the ABV process, particularly for generating SystemVerilog Assertions (SVAs) from design specification. In this paper, we provide an overview of recent works, highlighting the different methods used to generate SVAs. In particular, we investigate LLM-based SVA generation and ask a central question: How can LLM-based assertion generation be made systematic and quality-aware? While addressing this key question, we provide Key Takeaways at the end of each challenge, summarizing the important methodological insights, and also provide guidelines and directions in solving those challenges that can help generate a high-quality set of assertions using LLMs.  \nIndex Terms—LLM-based Verification, SystemVerilog Assertions, LLM, Design Verification  \nI. INTRODUCTION  \nDesign verification is a critical stage in the chip design flow, ensuring that an implementation satisfies its intended functional specification. Among different verification methodologies, assertion-based verification (ABV) is widely adopted as it allows design intent to be expressed as formal properties and checked against the RTL implementation. Traditionally, verification engineers manually write properties from design description and encode them as SystemVerilog Assertions (SVAs), while design engineers implement the RTL using a Hardware Description Language (HDL) . These SVAs specify the expected functionality of the design and verification tool verify whether the RTL implementation satisfies the specified properties. Manually writing SVAs is labour-intensive and complex, making it time-consuming and prone to human error. Therefore, researchers have now moved towards automatic assertion generation frameworks [1], [2] .  \nThe introduction of the Transformer architecture [3] by Google in 2017 has provided the foundation for modern Large Language Models (LLMs) . This progress has motivated the use of LLMs in ABV process, particularly focusing on generating functional SVAs automatically. Existing frameworks use diverse strategies for LLM-based assertion generation, including structured specification processing, multi-agent pipelines for information extraction and property generation, RTL-assisted prompting, and evaluation using different quality metrics. These variations raise an important question: How can  \nLLM-based assertion generation be made more systematic and quality-aware by effectively representing design information, including Natural Language Specifications (NLS) and RTL?. In this paper, we review existing LLM-based assertiongeneration works to characterize the current state of the field. Through this analysis, we identify key design choices, limitations, and requirements for developing more systematic and quality-aware LLM-based assertion-generation flows. The results and reports of the case studies performed can be found in [4] . The primary contributions of this paper are as follows:  \n• We provide a structured study of recent LLM-based assertion-generation frameworks, understanding their prompt inputs, generation strategies, refinement mechanisms, and evaluation methodologies.  \n• We identify critical quality challenges in LLM-generated assertions, including signal-name inconsistency, vacuous proofs, redundancy, incomplete functional coverage, and misleadin","cbCaiiF23y9kImnf","https://ap.wps.com/l/cbCaiiF23y9kImnf","pdf",233979,2,1,6,"English","en",105,"# Introduction\n## Assertion-based verification (ABV)\n## Motivation for LLM-assisted assertion generation\n# Challenges in LLM assisted assertion generation\n## Assertion checking: dynamic vs static\n## Specifications vs RTL\n# Guidelines and future directions\n# Conclusion","[{\"question\":\"Why is assertion-based verification (ABV) time-consuming in chip design verification?\",\"answer\":\"ABV typically relies on verification engineers manually generating assertions from design specifications and encoding them as SystemVerilog Assertions (SVAs). This manual process is labor-intensive, complex, and prone to human error.\"},{\"question\":\"How do static and dynamic assertion checking differ?\",\"answer\":\"Dynamic ABV evaluates assertions over simulation traces, while static ABV (formal property verification) uses formal tools to exhaustively check whether properties hold over all reachable behaviors using a constructed state-space representation.\"},{\"question\":\"What makes LLM-based SVA generation a “systematic and quality-aware” problem?\",\"answer\":\"The paper highlights multiple quality challenges such as signal-name inconsistency, vacuous proofs, redundancy, incomplete functional coverage, and misleading coverage inflation, and proposes quality-aware mechanisms like vacuity analysis, coverage-based evaluation, and cone-of-influence (COI) analysis.\"}]",1784200091,15,{"code":4,"msg":31,"data":32},"ok",{"site_id":25,"language":24,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":86,"head_meta":88,"extra_data":90,"updated_unix":28},"llm-assisted-verification-assertion-generation-challenges-and-future-directions","",{"@graph":36,"@context":85},[37,53,68],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,47,50],{"item":41,"name":42,"@type":43,"position":21},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":20},"https://docshare.wps.com/document/","Document",{"item":48,"name":12,"@type":43,"position":49},"https://docshare.wps.com/document/research-report/",3,{"item":51,"name":13,"@type":43,"position":52},"https://docshare.wps.com/document/llm-assisted-verification-assertion-generation-challenges-and-future-directions/84993/",4,{"url":51,"name":13,"@type":54,"author":55,"headline":13,"publisher":57,"fileFormat":60,"inLanguage":24,"description":14,"dateModified":61,"datePublished":62,"encodingFormat":60,"isAccessibleForFree":63,"interactionStatistic":64},"DigitalDocument",{"name":9,"@type":56},"Person",{"url":41,"name":58,"@type":59},"DocShare","Organization","application/pdf","2026-07-23","2026-07-16",true,{"@type":65,"interactionType":66,"userInteractionCount":20},"InteractionCounter",{"@type":67},"ViewAction",{"@type":69,"mainEntity":70},"FAQPage",[71,77,81],{"name":72,"@type":73,"acceptedAnswer":74},"Why is assertion-based verification (ABV) time-consuming in chip design verification?","Question",{"text":75,"@type":76},"ABV typically relies on verification engineers manually generating assertions from design specifications and encoding them as SystemVerilog Assertions (SVAs). This manual process is labor-intensive, complex, and prone to human error.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"How do static and dynamic assertion checking differ?",{"text":80,"@type":76},"Dynamic ABV evaluates assertions over simulation traces, while static ABV (formal property verification) uses formal tools to exhaustively check whether properties hold over all reachable behaviors using a constructed state-space representation.",{"name":82,"@type":73,"acceptedAnswer":83},"What makes LLM-based SVA generation a “systematic and quality-aware” problem?",{"text":84,"@type":76},"The paper highlights multiple quality challenges such as signal-name inconsistency, vacuous proofs, redundancy, incomplete functional coverage, and misleading coverage inflation, and proposes quality-aware mechanisms like vacuity analysis, coverage-based evaluation, and cone-of-influence (COI) analysis.","https://schema.org",{"og:url":51,"og:type":87,"og:title":13,"og:site_name":58,"og:description":14},"article",{"robots":89,"canonical":51},"index,follow",{"doc_id":7,"site_id":25},{"code":4,"msg":5,"data":92},[93,97,101,105,110,114,119,122,127,130,134],{"id":21,"doc_module":4,"doc_module_name":46,"category_name":94,"show_sort_weight":95,"slug":96},"Story & Novel",90,"story-novel",{"id":20,"doc_module":4,"doc_module_name":46,"category_name":98,"show_sort_weight":99,"slug":100},"Literature",80,"literature",{"id":52,"doc_module":4,"doc_module_name":46,"category_name":102,"show_sort_weight":103,"slug":104},"Exam",70,"exam",{"id":106,"doc_module":4,"doc_module_name":46,"category_name":107,"show_sort_weight":108,"slug":109},5,"Comic",60,"comic",{"id":22,"doc_module":4,"doc_module_name":46,"category_name":111,"show_sort_weight":112,"slug":113},"Technology",50,"technology",{"id":115,"doc_module":4,"doc_module_name":46,"category_name":116,"show_sort_weight":117,"slug":118},7,"Healthcare",40,"healthcare",{"id":11,"doc_module":4,"doc_module_name":46,"category_name":12,"show_sort_weight":120,"slug":121},30,"research-report",{"id":123,"doc_module":4,"doc_module_name":46,"category_name":124,"show_sort_weight":125,"slug":126},9,"Religion & Spirituality",20,"religion-spirituality",{"id":125,"doc_module":4,"doc_module_name":46,"category_name":128,"show_sort_weight":125,"slug":129},"World Cup","world-cup",{"id":131,"doc_module":4,"doc_module_name":46,"category_name":132,"show_sort_weight":131,"slug":133},10,"Lifestyle","lifestyle",{"id":135,"doc_module":4,"doc_module_name":46,"category_name":136,"show_sort_weight":106,"slug":137},19,"General","general"]