[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-seo-657681-105":3,"detail-sidebar-cat-0-en-105":81,"doc-detail-657681-en":130},{"code":4,"msg":5,"data":6},0,"ok",{"site_id":7,"language":8,"slug":9,"title":10,"keywords":11,"description":12,"schema_data":13,"social_meta":74,"head_meta":76,"extra_data":78,"updated_unix":80},105,"en","lecture-3-logic-gates-ii","Lecture 3 - Logic Gates (II)","","Lecture 3 (Second Stage) on Digital Electronics focuses on universal and derived logic gate implementations, starting with the standard NAND gate and the bubbled OR gate realization using De Morgan’s theorem. It then develops basic gates (NOT, OR, AND) from NAND, followed by XOR and XNOR gate properties, truth tables, Boolean expressions, and practical implementation approaches. The lecture also covers XNOR with higher-order inputs via cascaded XOR trees and even-function behavior, plus example problems.",{"@graph":14,"@context":73},[15,34,56],{"@type":16,"itemListElement":17},"BreadcrumbList",[18,23,27,31],{"item":19,"name":20,"@type":21,"position":22},"https://docshare.wps.com","Home","ListItem",1,{"item":24,"name":25,"@type":21,"position":26},"https://docshare.wps.com/document/","Document",2,{"item":28,"name":29,"@type":21,"position":30},"https://docshare.wps.com/document/technology/","Technology",3,{"item":32,"name":10,"@type":21,"position":33},"https://docshare.wps.com/document/lecture-3-logic-gates-ii/657681/",4,{"url":32,"name":10,"@type":35,"image":36,"author":41,"headline":10,"publisher":44,"fileFormat":47,"inLanguage":8,"description":12,"dateModified":48,"datePublished":49,"encodingFormat":47,"isAccessibleForFree":50,"interactionStatistic":51},"DigitalDocument",{"url":37,"@type":38,"width":39,"height":40},"https://docshare.wps.com/thumbnails/lecture-3-logic-gates-ii/657681.png","ImageObject",300,407,{"name":42,"@type":43},"Ezra","Person",{"url":19,"name":45,"@type":46},"DocShare","Organization","application/pdf","2026-10-30","2026-10-26",true,{"@type":52,"interactionType":53,"userInteractionCount":55},"InteractionCounter",{"@type":54},"ViewAction",6,{"@type":57,"mainEntity":58},"FAQPage",[59,65,69],{"name":60,"@type":61,"acceptedAnswer":62},"How is the standard NAND gate related to the AND gate?","Question",{"text":63,"@type":64},"The NAND gate is implemented as an AND gate followed by an inverter, i.e., AND with a bubble at the output.","Answer",{"name":66,"@type":61,"acceptedAnswer":67},"What is the logical function of an XOR gate?",{"text":68,"@type":64},"An XOR gate performs modulo-2 addition: the output is 1 when inputs are different (01 or 10) and 0 when they are the same (00 or 11).",{"name":70,"@type":61,"acceptedAnswer":71},"How can an XNOR gate with 3 or more inputs be implemented?",{"text":72,"@type":64},"By cascading 2-input XOR gates in a tree format, except replacing the final XOR output gate with an XNOR gate.","https://schema.org",{"og:url":32,"og:type":75,"og:title":10,"og:site_name":45,"og:description":12},"article",{"robots":77,"canonical":32},"index,follow",{"doc_id":79,"site_id":7},657681,1793141165,{"code":4,"msg":82,"data":83},"success",[84,88,92,96,101,104,109,114,119,122,126],{"id":22,"doc_module":4,"doc_module_name":25,"category_name":85,"show_sort_weight":86,"slug":87},"Story & Novel",90,"story-novel",{"id":26,"doc_module":4,"doc_module_name":25,"category_name":89,"show_sort_weight":90,"slug":91},"Literature",80,"literature",{"id":33,"doc_module":4,"doc_module_name":25,"category_name":93,"show_sort_weight":94,"slug":95},"Exam",70,"exam",{"id":97,"doc_module":4,"doc_module_name":25,"category_name":98,"show_sort_weight":99,"slug":100},5,"Comic",60,"comic",{"id":55,"doc_module":4,"doc_module_name":25,"category_name":29,"show_sort_weight":102,"slug":103},50,"technology",{"id":105,"doc_module":4,"doc_module_name":25,"category_name":106,"show_sort_weight":107,"slug":108},7,"Healthcare",40,"healthcare",{"id":110,"doc_module":4,"doc_module_name":25,"category_name":111,"show_sort_weight":112,"slug":113},8,"Research & Report",30,"research-report",{"id":115,"doc_module":4,"doc_module_name":25,"category_name":116,"show_sort_weight":117,"slug":118},9,"Religion & Spirituality",20,"religion-spirituality",{"id":117,"doc_module":4,"doc_module_name":25,"category_name":120,"show_sort_weight":117,"slug":121},"World Cup","world-cup",{"id":123,"doc_module":4,"doc_module_name":25,"category_name":124,"show_sort_weight":123,"slug":125},10,"Lifestyle","lifestyle",{"id":127,"doc_module":4,"doc_module_name":25,"category_name":128,"show_sort_weight":97,"slug":129},19,"General","general",{"code":4,"msg":82,"data":131},{"doc_id":79,"user_id":132,"nickname":42,"user_avatar":133,"doc_module":4,"category_id":55,"category_name":29,"doc_title":10,"doc_description":12,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":55,"is_deleted":4,"is_public":22,"is_downloadable":22,"audit_status":22,"page_count":115,"language":139,"language_code":8,"site_id":7,"html_lang":8,"table_of_contents":140,"faqs":141,"seo_title":142,"seo_description":12,"update_tm":143,"read_time":144},1099514068035,"https://ap-avatar.wpscdn.com/davatar_276721f389ce27ea32af1340a28f341c","Lecture 3  \nSecond Stage  \nMedical Physical Department  \nDigital Electronics  \nLecture 3: Logic Gates (II)  \nBy  \nDr. Feral Ibrahim Althefery  \n| Logic Gates\u003Cbr>1. Universal Logic Gates\u003Cbr>1.1NAND Gate\u003Cbr>The standard NAND gate is AND gate followed by inverter i.e. AND gate with bubble at its output. Two or more inputs are associated with NAND gate and the gate has one output. The standardized symbol for NAND gate with two inputs (A & B), the output (Z) and the truth table are shown in Fig.1. ICs for standard NAND gate are available. The inputs and output of NAND gate are related by,\u003Cbr>\u003Cbr>Fig. 1 Standard NAND gate with two inputs\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>|  |  |\n| --- | --- | --- |\n| | 􀢆 = (􀡭 · 􀡮)′ | |\n| 1.1.1 Bubbled OR Gate\u003Cbr>NAND gate could also be realized by having inverters for the inputs of OR gate i.e. bubbled OR gate. The standardized symbol for bubbled OR gate with two inputs (A & B), the output (Z) and the truth table are shown in Fig.2. The inputsand output of bubbled OR gate are related by,\u003Cbr>\u003Cbr>Fig. 2 Bubbled OR gate with two inputs |  |  |\n\n| \u003Cbr>\u003Cbr>􀢆   =  􀡭 ′  +  􀡮 ′\u003Cbr>\u003Cbr>\u003Cbr>The outputs of standard NAND gate and bubbled OR gate are same for the same combination of input\u003Cbr>s. It could be proved by applying De Morgan’s theorem on the outputs.\u003Cbr>\u003Cbr>|  |  |\n| --- | --- | --- |\n| | 􀢆 = 􀡭 ′ + 􀡮 ′ = (􀡭 · 􀡮)′ | |\n| | 1.1.2 Basic Logic Gates from NAND Gate\u003Cbr>The three basic logic gates, NOT, OR and AND, could be realized from NAND gate. The logic circuits for realizing the gates are shown in Fig.3. The derivations for the output expressions for the gates are also shown in the figures. | |\n| | |  |\n| Fig.3 Basic logic gates from NAND gate\u003Cbr>2. The Exclusive-OR Gate (XOR Gate)\u003Cbr>The exclusive-OR gate performs modulo-2 addition. Standard symbols for an exclusive OR (X-OR) gate and Boolean expression for the output of a 2-input XOR gate can be written as:\u003Cbr>􀜳 = ̅􀜣􀜤 + 􀜣 ̅􀜤 = 􀜣 ⊕ 􀜤 |  |  |\n\nThe X-OR gate has only two inputs. The four possible input combinations and the resulting outputs f  \nor an X-OR gate. The operation of an X-OR gate is summarized in the truth table shown  \n2-input XOR Gate  \n\n| Symbol | Truth Table |  |  |\n| --- | --- | --- | --- |\n| \u003Cbr>2-input Ex-OR Gate | B | A | Q |\n|  | 0 | 0 | 0 |\n|  | 0 | 1 | 1 |\n|  | 1 | 0 | 1 |\n|  | 1 | 1 | 0 |\n| Boolean Expression Q = A ⊕ B | A OR B but NOT BOTH gives Q |  |  |\n\n| 3. Exclusive NOR-Gate (XNOR-Gate)\u003Cbr>XNOR (exclusive NOR) gate is XOR gate followed by inverter. The output of XNOR gate is the complement of the output of XOR gate. Standard ICs (Ex. 74LS266, Quad 2-input XNOR) are available for XNOR gates with two inputs.\u003Cbr>The output of 2-input\u003Cbr>when both the inputs are either Low or High; otherwise, the output is Low. XNOR gate could be implemented by using appropriate combination of inverter, AND, OR, NOR and NAND gates. 2-input XNOR gate could be conveniently implemented using Quad 2-input NOR gate. The NOR gate implementation, the symbol and the truth table of XNOR gate are shown in Fig. 4. The operator,⨀,represents XNOR operation. The inputs and output of 2-input XNOR function are related by,\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>|\n| --- |\n| \u003Cbr>|\n| \u003Cbr>|\n\n| Fig. 4 Implementation of 2-input XNOR gate\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>\u003Cbr>|  |  |\n| --- | --- | --- |\n| | 􀢆 = (􀡭 ⨀ 􀡮) = (􀡭 ⊕ 􀡮)′ = 􀡭 · 􀡮 + 􀡭 ′ · 􀡮 ′ | |\n| | 3.1 XNOR with Higher Order Inputs\u003Cbr>XNOR function for 3 or more inputs (variables) is implemented by cascading 2-input XOR gates in a tree format except that the output XOR gate is replaced by XNOR gate. The implementation of 3-input and 4-input XNOR","cbCaitOQ3iacjuah","https://ap.wps.com/l/cbCaitOQ3iacjuah","pdf",823726,"English","# Logic Gates (II)\n## Universal Logic Gates\n### NAND Gate\n### Bubbled OR Gate\n### Basic Logic Gates from NAND Gate\n## Exclusive-OR Gate (XOR Gate)\n## Exclusive NOR-Gate (XNOR Gate)\n## XNOR with Higher Order Inputs\n## Even Function\n## Implementation of Gates Using NAND Gate\n## Examples and Exercises","[{\"question\":\"How is the standard NAND gate related to the AND gate?\",\"answer\":\"The NAND gate is implemented as an AND gate followed by an inverter, i.e., AND with a bubble at the output.\"},{\"question\":\"What is the logical function of an XOR gate?\",\"answer\":\"An XOR gate performs modulo-2 addition: the output is 1 when inputs are different (01 or 10) and 0 when they are the same (00 or 11).\"},{\"question\":\"How can an XNOR gate with 3 or more inputs be implemented?\",\"answer\":\"By cascading 2-input XOR gates in a tree format, except replacing the final XOR output gate with an XNOR gate.\"}]","Lecture 3 - Logic Gates (II) | PDF",1792986267,23]