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Learning outcomes include understanding the relationship between behavior and construction criteria, describing advanced digital systems at multiple abstraction levels, and performing simulation and synthesis. The lesson goals introduce state machines and key variants, covering Moore and Mealy types, specification using state tables, state diagrams, ASM diagrams, and VHDL, followed by guidance on FSM motivation, representations, and example direction.",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":20,"@type":76,"position":81},"https://docshare.wps.com/document/exam/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/in3160-finite-state-machines-course-goals-and-learning-outcome/657536/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/in3160-finite-state-machines-course-goals-and-learning-outcome/657536.png","ImageObject",300,407,{"name":92,"@type":93},"Jacob","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-29","2026-10-26",true,{"@type":102,"interactionType":103,"userInteractionCount":8},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"What are the key learning outcomes for this finite state machines course?","Question",{"text":112,"@type":113},"After completion, learners can understand principles for design and testing, explain the relationship between behavior and construction criteria, describe advanced digital systems at different levels of detail, and perform simulation and synthesis.","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"How do Moore and Mealy state machines differ in output behavior?",{"text":117,"@type":113},"Moore machine outputs are decoded entirely from state registers, while Mealy machine outputs are decoded from input and state registers.",{"name":119,"@type":110,"acceptedAnswer":120},"How can hazards and delays be handled in synchronized Mealy designs?",{"text":121,"@type":113},"The materials present input and output synchronizers; the solution uses fully synchronized Mealy FSM concepts where input/output synchronization removes hazards while maintaining minimum delay within the state machine design.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},657536,1792982369,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":133,"doc_module":4,"category_id":19,"category_name":20,"doc_title":65,"doc_description":67,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":8,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":139,"language":140,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":141,"faqs":142,"seo_title":143,"seo_description":67,"update_tm":129,"read_time":144},962084931830,"https://ap-avatar.wpscdn.com/davatar_a8503ba1806abce46bf441b54a3ca4cd","IN3160 IN4160  \nFinite State Machines  \nYngve Hafting  \nMessages  \n• Assignment 6  \n– beta is posted  \n– Progress in 6, 8 and 10 are tied  \n– Read specifications, not only task  \n– Start early (greater task = longer time)  \n• FSM-videos from 2017 re-posted with text (autotext)  \n– Mostly very good (se last pages)  \n– use the newer source code for reference:  \n•  [https://www.uio.no/studier/emner/matnat/ifi/](https://www.uio.no/studier/emner/matnat/ifi/IN3160/v23/fsm-videoer/src-traffic.zip)[IN3160/v23/fsm-videoer/src-traffic.zip](https://www.uio.no/studier/emner/matnat/ifi/IN3160/v23/fsm-videoer/src-traffic.zip)  \nCourse Goals and Learning Outcome  \n[https://www.uio.no/studier/emner/matnat/ifi/IN3160/index-eng.html](https://www.uio.no/studier/emner/matnat/ifi/IN3160/index-eng.html)  \nIn this course you will learn about the design of advanced digital systems. This includes programmable logic circuits, a hardware design language and system-on-chip design (processor, memory and logic on a chip) . Lab assignments provide practical experience in how real design can be made.  \nAfter completion of the course you will:  \n• understand important principles for design and testing of digital systems  \n• understand the relationship between behaviour and different construction criteria  \n• be able to describe advanced digital systems at different levels of detail  \n• be able to perform simulation and synthesis of digital systems.  \nGoals for this lesson:  \n• Know different types of state machines  \n• What is a state machine  \n• Moore type machines  \n• Mealy type machines  \n• To specify state machine functionality using  \n• State tables  \n• State diagrams  \n• Algorithic state machine diagrams  \n• VHDL  \n• To know pro’s and con’s for  \n• Moore and Mealy  \n• Different state machine representations  \nOverview Today  \n• What is finite state machines (FSM)?  \n– General FSM  \n– Moore type FSM  \n– Mealy  \n– Synchronized Mealy  \n• FSM representations  \n– State diagram  \n– State output table  \n– Algorithmic State Machine (ASM) diagrams  \n• FSM example with VHDL and testbench  \nNext:  \n• Datapath state machines  \nWhy/What is an FSM?  \n• Names  \n– Finite State Machine \"FSM\"  \n– Finite State Automaton \"FSA\"  \n– State Machine (Never seen \"SM\" used for this)  \n– Finite automaton  \n• A description of something that happens in a more or less fixed sequence  \n– Going through a set of states  \n• Not an FSM? \"ISM\" / \"ESM\"?  \n– Near infinite or endless amount of states...  \n• Any computer program could be called an \"FSM\",  \n– we do not use the term FSM for SW in general  \n• Example FSM?  \n– Traffic light implementation  \n– Pushbutton user interfaces  \n• Vending machine  \n• Washing machine program  \n– Bus controller  \n– Arbitration algorithm  \n– Microprocessors, etc  \n• FSMs can be made in HW, FW or SW. (We'll cover HW)  \nGeneral FSM in HW  \n• General FSM  \n– Combinational logic connected to registers with feedback  \n– Can be nearly any clocked logic  \n• Counter  \n• LFSR  \n• Shiftregister  \n• Timer  \n• Microprocessor  \n• Vending machines…  \n• Etc.  \nCombinational logic  \nInput State  \n\n| D\u003Cbr>| Q\u003Cbr>CLK |\n| --- | --- |\n\n\n|  | D\u003Cbr>| Q\u003Cbr>CLK | |\n| --- | --- | --- | --- |\n|  |  |  |  |\n\nCombinational  \nlogic  \n7  \nNon FSM sequental logic?  \n• Strictly speaking any logic using registers (FFs) are FSMs , but…  \n• We usually don’t refer to things as FSMs when they  \n– Have well known names or near-infinite states  \n• Shift registers,  \n• Counters , Timers  \n• LFSR (linear feedback shift registers)  \n• Microprocessors •    \n– are pure datapath representations  \n| D\u003Cbr>| Q\u003Cbr>CLK |\n| --- | --- |\n\nouput  \n• No feedback after registers 8  \nOutput decoding in FSM  \n• Two types:  \n– Moore  \n• Output is entirely decoded from state registers  \n– Mealy  \n• Output is decoded from input and state registers  \nInput  \nOutput  \nCombinational  \nlogic  \nCombinational  \nlogic  \nMealy FSM  \nOutput  \nCL  \nState CL  \n• Fast output  \n ! •• AsHayznchrardso! nous output!  \nMoore FSM  \n• O","cbCaimo0b6nGw8Mj","https://ap.wps.com/l/cbCaimo0b6nGw8Mj","pdf",1603979,41,"English","# Messages\n# Course Goals and Learning Outcome\n# Goals for this lesson\n# Overview Today\n# Why/What is an FSM?\n# General FSM in HW\n# Combinational logic and non-FSM sequential logic\n# Output decoding in FSM (Moore vs Mealy)\n# Input synchronizer and output synchronizer\n# Fully synchronized Mealy FSM","[{\"question\":\"What are the key learning outcomes for this finite state machines course?\",\"answer\":\"After completion, learners can understand principles for design and testing, explain the relationship between behavior and construction criteria, describe advanced digital systems at different levels of detail, and perform simulation and synthesis.\"},{\"question\":\"How do Moore and Mealy state machines differ in output behavior?\",\"answer\":\"Moore machine outputs are decoded entirely from state registers, while Mealy machine outputs are decoded from input and state registers.\"},{\"question\":\"How can hazards and delays be handled in synchronized Mealy designs?\",\"answer\":\"The materials present input and output synchronizers; the solution uses fully synchronized Mealy FSM concepts where input/output synchronization removes hazards while maintaining minimum delay within the state machine design.\"}]","IN3160 - Finite State Machines - Course Goals and Learning Outcome | PDF",103]