[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-120793-en":3,"doc-seo-120793-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},120793,8796095360427,"Lucas Martin","https://ap-avatar.wpscdn.com/davatar_994ba38a5ba835b3df7d355c54d3ed8d",6,"Technology","In-Memory Computing for Machine Learning and Deep Learning","In-memory computing (IMC) executes numerical operations through physical processes such as current summation and charge collection, targeting acceleration of compute-intensive tasks like matrix-vector multiplication. Despite strong promise for memory-heavy workloads in machine learning and deep learning, IMC implementations must address major device and circuit nonidealities that affect accuracy. The work surveys research trends and implementation options for deep learning accelerators using emerging memory technologies, covering device technologies, computing primitives, and digital/analog/mixed design approaches, and then benchmarks key metrics and device issues.","Received 8 March 2023; accepted 3 April 2023. Date of publication 17 April 2023; date of current version 3 November 2023.  \nThe review of this article was arranged by Editor K. Ota.  \nDigital Object Identifier 10.1109/JEDS.2023.3265875  \nIn-Memory Computing for Machine Learning and Deep Learning  \nN. LEPRI (Graduate Student Member, IEEE), A. GLUKHOV (Graduate Student Member, IEEE),  \nL. CATTANEO(Graduate Student Member, IEEE), M. FARRONATO (Graduate Student Member, IEEE),  \nP. MANNOCCI (Graduate Student Member, IEEE), AND D. IELMINI (Fellow, IEEE)  \nDipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano and IU.NET, 20133 Milan, Italy  \nCORRESPONDING AUTHOR: D. IELMINI (e-mail: [daniele.ielmini@polimi.it](daniele.ielmini@polimi.it))  \nThis work was supported by the EU’s Horizon Europe Research and Innovation Programme under Grant 101070679 .  \nABSTRACT In-memory computing (IMC) aims at executing numerical operations via physical processes, such as current summation and charge collection, thus accelerating common computing tasks including the matrix-vector multiplication. While extremely promising for memory-intensive processing such as machine learning and deep learning, the IMC design and realization must face significant challenges due to device and circuit nonidealities. This work provides an overview of the research trends and options for IMCbased implementations of deep learning accelerators with emerging memory technologies. The device technologies, the computing primitives, and the digital/analog/mixed design approaches are presented. Finally, the major device issues and metrics for IMC are discussed and benchmarked.  \nINDEX TERMS In-memory computing, deep learning, deep neural network, emerging memory technologies, matrix-vector multiplication.  \nI. INTRODUCTION  \nToday, artificial intelligence and its enabling technology, the deep neural networks (DNN), have become largely popular in various applications such as image recognition, autonomous vehicles, speech recognition, and natural language processing. In the last five years, a state-of-the-art deep neural network model increased the number of its parameters by about 4 orders of magnitude, leading to a significant increase in computational and memory requirements for both the training and the inference operations [1], [2], [3], [4], [5],[6] . Traditional computing systems (Fig. 1a) typically store massive information on a memory unit that is physically connected to the computational unit by a data bus. The continuous data movement between the processing and the memory units represents the main bottleneck due to the limited bandwidth, long latency, sequential data processing, and high energy consumption [7], [8] .  \nTo minimize the latency and energy overhead of conventional von Neumann computers, in-memory computing (IMC) aims at performing the computation in close proximity to the memory or even in situ within the memory  \nitself [9], [10] . The range of operations that can be executed within memory devices includes stateful logic [11],[12], pulse integration [13], [14], associative memory [15],[16], and stochastic computing [17] . The most popular and enabling IMC operation is, however, matrix-vector multiplication (MVM) via Ohm’s and Kirchhoff’s law in a memory array [18], [19] . IMC has been thus largely targeted for hardware accelerators of DNN, where MVM is by far the most intensive workload. The ability to execute MVM in a single operation by activating all rows and all columns in parallel represents a key benefit of IMC that is unrivaled by other technologies. Despite the simplicity of the MVM concept and the potential advantages of IMC, the design options and the interaction between circuit operation and  \ndevice nonidealities still represent a key open challenge.  \nThis work provides an overview of IMC for DNN acceleration from the perspectives of device technology, circuit design, device-circuit interaction, and its impact on compu","cbCaikgVC9v4HdMi","https://ap.wps.com/l/cbCaikgVC9v4HdMi","pdf",3413704,1,15,"English","en",105,"# Introduction\n## Computational bottlenecks in von Neumann systems\n## Core IMC principles and supported operations\n## Matrix-vector multiplication as the enabling IMC workload\n# Computational Memory Technologies\n## Near-memory computing and embedded memory options\n# IMC circuit topologies and applications\n# IMC acceleration for DNN inference\n# Device nonidealities and accuracy impact\n# Open challenges and future directions\n# Conclusion","[{\"question\":\"What is the main goal of in-memory computing for deep learning workloads?\",\"answer\":\"It aims to perform numerical operations close to the memory or inside the memory itself, reducing data movement and accelerating compute-heavy tasks such as matrix-vector multiplication.\"},{\"question\":\"Which operation is described as the most enabling IMC workload?\",\"answer\":\"Matrix-vector multiplication (MVM), implemented using physical laws (Ohm’s and Kirchhoff’s law) in a memory array, enabling parallel activation of rows and columns.\"},{\"question\":\"Why do IMC designs face challenges for accurate deep learning acceleration?\",\"answer\":\"IMC implementations must handle significant device and circuit nonidealities that can degrade computing accuracy, so device issues and metrics are discussed and benchmarked.\"}]","In-Memory Computing for Machine Learning and Deep Learning | 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is the main goal of in-memory computing for deep learning workloads?","Question",{"text":75,"@type":76},"It aims to perform numerical operations close to the memory or inside the memory itself, reducing data movement and accelerating compute-heavy tasks such as matrix-vector multiplication.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"Which operation is described as the most enabling IMC workload?",{"text":80,"@type":76},"Matrix-vector multiplication (MVM), implemented using physical laws (Ohm’s and Kirchhoff’s law) in a memory array, enabling parallel activation of rows and columns.",{"name":82,"@type":73,"acceptedAnswer":83},"Why do IMC designs face challenges for accurate deep learning acceleration?",{"text":84,"@type":76},"IMC implementations must handle significant device and circuit nonidealities that can degrade computing accuracy, so device issues and metrics are discussed and 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