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The prototype is implemented in 65-nm CMOS at 1-V, achieving 1.9-ps resolution at 2.5-GS/s. Simulated DNL is 0.85-LSB and INL is 0.64-LSB. The PI-TDC is used in a high-speed TB-ADC with a high-performance VTC and CCS-CAL, yielding 8-bit at 1.6-GS/s with PVT robustness and 52.1-fJ/conv.-step (Walden FoM).",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":40,"@type":76,"position":81},"https://docshare.wps.com/document/research-report/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/ieice-electronics-express-vol20-no3-19-ps-8-phase-interpolation-tdc-with-capacitance-compensation-self-calibration/290432/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/ieice-electronics-express-vol20-no3-19-ps-8-phase-interpolation-tdc-with-capacitance-compensation-self-calibration/290432.png","ImageObject",300,407,{"name":92,"@type":93},"Jake","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-11-04","2026-09-17",true,{"@type":102,"interactionType":103,"userInteractionCount":52},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"What is the main function of the proposed PI-TDC architecture?","Question",{"text":112,"@type":113},"It converts time intervals using an 8-phase interpolation approach to enhance both resolution and conversion speed, supported by high-frequency readout and reset techniques.","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"What circuit and performance targets does the prototype achieve?",{"text":117,"@type":113},"The PI-TDC prototype is implemented in 65-nm CMOS with a 1-V supply, achieving 1.9-ps resolution at 2.5-GS/s, with simulated DNL of 0.85-LSB and INL of 0.64-LSB.",{"name":119,"@type":110,"acceptedAnswer":120},"How is the PI-TDC used in the TB-ADC, and what benefits are reported?",{"text":121,"@type":113},"It is applied to a high-speed TB-ADC combined with a VTC and CCS-CAL, achieving 8-bit at 1.6-GS/s with PVT robustness and a Walden FoM of 52.1-fJ/conv.-step.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},290432,1789641675,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":133,"doc_module":4,"category_id":39,"category_name":40,"doc_title":65,"doc_description":67,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":52,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":24,"language":139,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":140,"faqs":141,"seo_title":142,"seo_description":67,"update_tm":129,"read_time":143,"preview_page_count":4},962084928904,"https://ap-avatar.wpscdn.com/davatar_155a257f0dc6eb9ab79c44ca47cae57d","IEICE Electronics Express, Vol.20, No.3, 1–5  \nLETTER  \nA 1.9-ps 8􀀂 phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration  \nZhijie Chen 1 , Xiaoyu Zhang 1 , Yongkuo Ma 1 , Xitong Liang 1 , Xinyu Du 1 , and Peiyuan Wan 1, a)  \nAbstract This paper presents a 1.9-ps 8􀀂 phase interpolation time-todigital converter (PI-TDC) . This architecture enhances the resolution and conversion speed in cooperation with phase interpolation, high-frequency readout, and reset techniques. The prototype PI-TDC is designed in a 65-nm CMOS process with a 1-V power supply, achieving a 1.9-ps resolution at 2 .5-GS/s. The simulated DNL is 0 . 85-LSB, and INL is 0 .64-LSB. This PI-TDC is applied to a high-speed time-based analog-to-digital converter (TB-ADC) with a high-performance voltage-to-time converter (VTC) and the capacitance compensation self-calibration (CCS-CAL) . The high-speed TB-ADC achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting a Walden FoM of 52.1-fJ/conv.-step.  \nKeywords: time-to-digital converter (TDC), phase interpolation (PI), voltage-to-time converter (VTC), analog-to-digital converter (ADC), capacitance compensation self-calibration (CCS-CAL), process, voltage, and temperature (PVT) robustness  \nClassification: Integrated circuits  \n1. Introduction  \nAfter decades of unremitting efforts, convincing new evidence shows that Moore’s Law has almost reached its limit. The “time for space” method has attracted more attention in the design of ultra-deep submicron mixed-signal circuits. The time-to-digital converter (TDC) plays the vital role in data conversion. It is usually applied to measure precise time intervals and provides time-domain solutions for frequency generation and data conversion, such as digital phase-locked loops (DPLL) [1, 2, 3] and time-based analog-to-digital converter (TB-ADC) [4, 5, 6, 7] .  \nThe delay-line TDC [8, 9, 10, 11, 12] is the most elementary structure with the merit of simple structure and low power. However, the inherent latency limits the resolution, making it challenging to achieve high-resolution TDC. The Vernier TDC [13, 14, 15, 16] adds an extra delay-line and expands the resolution. Based on Vernier TDC, two-dimensional (2-D) Vernier TDC [17, 18, 19], three-dimensional Vernier TDC [20], and Vernier ring TDC [21, 22] are derived. Two-step TDC [23, 24, 25] improves the speed of Vernier TDC by introducing a time amplifier (TA) . However, the gain of the TA is greatly affected by the process, voltage, and temperature (PVT) . The phase interpolation (PI) technique generates extra time signals, gated  \n1 Faculty of Information Technology, Beijing University of Technology, Chaoyang District, Beijing, 100124, China  \na) [wanpy@bjut.edu.cn](wanpy@bjut.edu.cn)  \nDOI: 10.1587/elex.20.20220515  \nReceived November 22, 2022  \nAccepted December 19, 2022  \nPublicized January 5, 2023  \nCopyedited February 10, 2023  \ninverter PI [26, 27, 28] and voltage division PI [28] are popular. The PI was applied to the delay cell [29], but plenty of PI cells lead to a larger area and higher power consumption. The number of interpolators is reduced by the 4􀀂 PI and 2-D quantization techniques [30] . There is also a restriction between speed and resolution in the above research on TDC.  \nThis paper proposed a 1.9-ps 8􀀂 PI-TDC under a 1-V power supply at 2.5-GS/s. The speed and resolution have been enhanced in cooperation with the PI, high-frequency readout, and reset techniques. Taking advantage of speed, the proposed 8􀀂 PI-TDC is applied to a high-speed TBADC in combination with a high-performance voltage-totime converter (VTC) and the capacitance compensation self-calibration (CCS-CAL) . The proposed high-speed TBADC under a 1-V power supply achieves 8-bit at 1.6-GS/s with PVT robustness while exhibiting an SNDR of 47.4-dBand a Walden FoM of 52.1-fJ/conv.-step. With the selfcalibration technique, the TB-ADC presents a sub-0.5-bit ENOB drop across a temperat","cbCaioLuvYqaD3Qt","https://ap.wps.com/l/cbCaioLuvYqaD3Qt","pdf",4683942,"English","# Introduction\n# Proposed technique\n## 8-phase phase interpolation TDC","[{\"question\":\"What is the main function of the proposed PI-TDC architecture?\",\"answer\":\"It converts time intervals using an 8-phase interpolation approach to enhance both resolution and conversion speed, supported by high-frequency readout and reset techniques.\"},{\"question\":\"What circuit and performance targets does the prototype achieve?\",\"answer\":\"The PI-TDC prototype is implemented in 65-nm CMOS with a 1-V supply, achieving 1.9-ps resolution at 2.5-GS/s, with simulated DNL of 0.85-LSB and INL of 0.64-LSB.\"},{\"question\":\"How is the PI-TDC used in the TB-ADC, and what benefits are reported?\",\"answer\":\"It is applied to a high-speed TB-ADC combined with a VTC and CCS-CAL, achieving 8-bit at 1.6-GS/s with PVT robustness and a Walden FoM of 52.1-fJ/conv.-step.\"}]","IEICE Electronics Express - Vol.20 No.3 - 1.9-ps 8-phase interpolation TDC with capacitance compensation self-calibration | PDF",13]