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Computer Science & Information Engineering, National Taiwan University, 5Netease, Hangzhou, China, 6 College of information Engineering, Capital Normal University, Beijing, China  \n1 fwangzhe12, lijianjun, wucg, [wangzhenjiang](wangzhenjiangg@ict.ac.cn)[g](wangzhenjiangg@ict.ac.cn)[@ict.ac.cn](wangzhenjiangg@ict.ac.cn) , [3](3 dyyang@cn.ibm.com)[ dyyang@cn.ibm.com](3 dyyang@cn.ibm.com) , [4](4 hsuwc@csie.ntu.edu.tw)[ hsuwc@csie.ntu.edu.tw](4 hsuwc@csie.ntu.edu.tw) ,  \n[5](5 richardustc@gmail.com)[ richardustc@gmail.com](5 richardustc@gmail.com) , [6](6 guanyong@mail.cnu.edu.cn)[ guanyong@mail.cnu.edu.cn](6 guanyong@mail.cnu.edu.cn)  \nAbstract  \nCross-ISA (Instruction Set Architecture) system-level virtual machine has a significant research and practical value. For example, several recently announced virtual smartphones for iOS which run smart phone applications on x86 based PCs are deployed on cross-ISA system level virtual machines. Also, for mobile device application development, by emulating the Android/ARM environment on the more powerful x86-64 platform, application development and debugging become more convenient and productive. However, the virtualization layer often incurs high performance overhead. The key overhead comes from memory virtualization where a guest virtual address (GVA) must go through multilevel address translation to become a host physical address (HPA) . The Embedded Shadow Page Table (ESPT) approach has been proposed to effectively decrease this address translation cost. ESPT directly maps GVA to HPA, thus avoid the lengthy guest virtual to guest physical, guest physical to host virtual, and host virtual to host physical address translation.  \n􀀃 To whom correspondence should be addressed.  \ny This work was done when Dongyan Yang attended Institute of Computing Technology, CAS.  \nz This work was done when Bin Li attended Institute of Computing Technology, CAS.  \nPermission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions [from permissions@acm.org](from permissions@acm.org).  \nVEE '15, March 14–15, 2015, Istanbul, Turkey.  \nCopyright 􀀍c 2015 ACM 978-1-4503-3450-1/15/03. . . $15.00 . [http://dx.doi.org/10.1145/2731186.2731188](http://dx.doi.org/10.1145/2731186.2731188)  \nHowever, the original ESPT work has a few drawbacks. For example, its implementation relies on a loadable kernel module (LKM) to manage the shadow page table. Using LKMs is less desirable for system virtual machines due to portability, security and maintainability concerns. Our work proposes a different, yet more practical, implementation to address the shortcomings. Instead of relying on using LKMs, our approach adopts a shared memory mapping scheme to maintain the shadow page table (SPT) using only “mmap”system call. Furthermore, this work studies the support of SPT for multi-processing in greater details. It devices three different SPT organizations and evaluates their strength and weakness with standard and real Android applications on the system virtual machine which emulates the Andro","cbCaihtV1H6Prsn0","https://ap.wps.com/l/cbCaihtV1H6Prsn0","pdf",1017845,12,"English","# Abstract\n# Introduction\n## Memory virtualization and address translation overhead\n## Cross-ISA system virtualization overview\n# Categories and Subject Descriptors\n# General Terms\n# Keywords","[{\"question\":\"Why does cross-ISA system-level virtualization incur high overhead?\",\"answer\":\"It often incurs performance overhead due to memory virtualization, where a guest virtual address must undergo multilevel address translation to become a host physical address.\"},{\"question\":\"How does Embedded Shadow Page Tables (ESPT) reduce address-translation cost?\",\"answer\":\"ESPT directly maps the guest virtual address (GVA) to the host physical address (HPA), avoiding the lengthy multi-step translations among guest and host virtual/physical addresses.\"},{\"question\":\"What problem does the proposed work address compared with the original ESPT approach?\",\"answer\":\"The original implementation relies on a loadable kernel module, which raises portability, security, and maintainability concerns. The proposed approach uses a shared memory mapping scheme maintained via only the mmap system call.\"}]","HSPT - Practical Implementation and Efficient Management of Embedded Shadow Page Tables for Cross-ISA System Virtual Machines | PDF",1789470371]