[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-84117-en":3,"doc-seo-84117-105":29,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":13,"seo_description":14,"update_tm":27,"read_time":28},84117,687197207057,"Sage","https://ap-avatar.wpscdn.com/davatar_29158cc5080c5b710cf443261637dec0",8,"Research & Report","Hardware-Aware Open-Source Framework for Design Space Exploration of Mixed-Signal Spiking Neural Networks","Energy-efficient neuromorphic computing at the edge demands simulation tools that reflect non-ideal mixed-signal spiking neural network (SNN) hardware while enabling system-level design space exploration. The work introduces an open-source hardware-aware simulation framework supporting neuron-model diversity (LIF, Hodgkin-Huxley, Axon-Hillock) and non-volatile analog synapses using floating-gate transistors and ReRAM. Device-level nonlinearities are integrated into PyTorch training and inference to optimize physical synaptic parameters. Evaluation on N-MNIST, DVS Gesture, and SHD reports classification accuracy plus hardware metrics (silicon area, power, quantization sensitivity), enabling cross-layer searches under application constraints.","arXiv :2607 .06456v2 [ ee ss . SP] 11 Jul 2026  \nA Hardware-Aware Open-Source Framework for Design Space Exploration of Mixed-Signal Spiking Neural Networks  \nSayma Nowshin Chowdhury 1 ,†, Vineeta Nair 1 ,†, Taseen Forhad 1 ,†, Aishwarya Natarajan2 , Corey Hart3 , Sahil Shah 1 ,∗  \n1 Department of Electrical and Computer Engineering, University of Maryland, College Park, MD, USA  \n2 Hewlett Packard Labs, USA  \n3 Lockheed Martin, USA  \nE-mail: [[sshah389@umd.edu](sshah389@umd.edu)]([mailto:sshah389@umd.edu](mailto:sshah389@umd.edu) )  \n† These authors contributed equally to this work.  \n∗ Corresponding author.  \nJune 2026  \nAbstract. Energy-efficient neuromorphic computing at the edge requires simulation tools that can capture the non-ideal behavior of mixed-signal spiking neural network (SNN) hardware while supporting system-level design exploration. This work presentsan open-source hardware-aware simulation framework for mixed-signal SNNs that enables comparative analysis across neuron, synapse and architecture choices. The framework supports multiple neuron models, including Leaky Integrate-and-Fire (LIF), Hodgkin-Huxley (HH) and Axon-Hillock (AH), together with non-volatile analog synapses based on floating-gate transistors and ReRAM devices. By incorporating device-level nonlinearities directly into PyTorch-based training and inference, the tool enables optimization of physical synaptic parameters rather than idealized abstract weights. The framework is evaluated on standard neuromorphic benchmarks, including N-MNIST, DVS Gesture and Spiking Heidelberg Digits (SHD) . For each model dataset configuration, it reports classification accuracy together with hardwareoriented metrics such as silicon area, power consumption and quantization sensitivity. These capabilities enable cross-layer design space exploration and help identify neuronsynapse configurations that best satisfy application-specific constraints on accuracy, energy efficiency, area and hardware fidelity.  \n1. Introduction  \nEdge devices support a wide range of applications, including remote monitoring and sensing, continuous vital-sign and physiological-signal monitoring and autonomous ground and aerial robots operating in unknown environments [1] . The data generated by these sensors are increasingly processed using machine learning algorithms. However, edge devices are severely constrained by size, weight, area and power (SWAP),  \nHardware-Aware SNN Design Framework 2  \nmotivating the exploration of new circuit and system architectures that can efficiently process sensor data at the edge.  \nNeuromorphic architectures, particularly spiking neural networks (SNNs), offer a promising approach for energy-efficient edge intelligence by drawing inspiration from the event-driven operation of the brain. Unlike conventional rate-encoded neural networks, SNNs operate through discrete spike events that closely mirror the temporal dynamics of biological neurons, offering inherent advantages in energy efficiency and temporal information processing [2, 3] . This event-driven computation model becomes particularly compelling when implemented on neuromorphic hardware platforms, where the spatially co-located memory and compute elements enable significantly higher energy efficiency compared to traditional von Neumann architectures [4–7] . The biological plausibility of SNNs extends beyond their spike-based communication to encompass local learning mechanisms such as spike-timing dependent plasticity (STDP) [8], which demonstrate substantially lower memory requirements and power consumption compared to conventional error backpropagation algorithms.  \nFigure 1: Impact of hardware non-idealities on neuromorphic learning and inference:(a) Software training assumes ideal linear weight behavior, also (b) assumed standard (software) training leads to narrow minima sensitive to hardware mismatches and nonlinearities. Consequently, (c) direct deployment of SnnTorch-trained weights onto the float","cbCaifkd6BrOFb3P","https://ap.wps.com/l/cbCaifkd6BrOFb3P","pdf",6980981,1,35,"English","en",105,"# Introduction\n## Energy-efficient edge neuromorphic context\n## Gap between software training and mixed-signal hardware\n## Motivation for hardware-aware exploration tools","[{\"question\":\"What problem does the framework address in mixed-signal spiking neural network deployment?\",\"answer\":\"It addresses the performance gap caused by hardware non-idealities such as nonlinearities, device mismatch, and process variations, which degrade accuracy when software-trained parameters are mapped directly to analog neuromorphic hardware.\"},{\"question\":\"Which neuron and synapse models are supported by the proposed framework?\",\"answer\":\"It supports multiple neuron models including LIF, Hodgkin-Huxley, and Axon-Hillock, and non-volatile analog synapses implemented with floating-gate transistors and ReRAM devices.\"},{\"question\":\"How does hardware-aware training differ from conventional software training in this framework?\",\"answer\":\"The framework incorporates device-level nonlinearities directly into PyTorch-based training and inference, enabling optimization of physical synaptic parameters rather than idealized abstract weights, improving robustness to hardware mismatches.\"}]",1784192976,88,{"code":4,"msg":30,"data":31},"ok",{"site_id":24,"language":23,"slug":32,"title":13,"keywords":33,"description":14,"schema_data":34,"social_meta":86,"head_meta":88,"extra_data":90,"updated_unix":27},"hardware-aware-open-source-framework-for-design-space-exploration-of-mixed-signal-spiking-neural-networks","",{"@graph":35,"@context":85},[36,53,68],{"@type":37,"itemListElement":38},"BreadcrumbList",[39,43,47,50],{"item":40,"name":41,"@type":42,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":44,"name":45,"@type":42,"position":46},"https://docshare.wps.com/document/","Document",2,{"item":48,"name":12,"@type":42,"position":49},"https://docshare.wps.com/document/research-report/",3,{"item":51,"name":13,"@type":42,"position":52},"https://docshare.wps.com/document/hardware-aware-open-source-framework-for-design-space-exploration-of-mixed-signal-spiking-neural-networks/84117/",4,{"url":51,"name":13,"@type":54,"author":55,"headline":13,"publisher":57,"fileFormat":60,"inLanguage":23,"description":14,"dateModified":61,"datePublished":62,"encodingFormat":60,"isAccessibleForFree":63,"interactionStatistic":64},"DigitalDocument",{"name":9,"@type":56},"Person",{"url":40,"name":58,"@type":59},"DocShare","Organization","application/pdf","2026-07-17","2026-07-16",true,{"@type":65,"interactionType":66,"userInteractionCount":20},"InteractionCounter",{"@type":67},"ViewAction",{"@type":69,"mainEntity":70},"FAQPage",[71,77,81],{"name":72,"@type":73,"acceptedAnswer":74},"What problem does the framework address in mixed-signal spiking neural network deployment?","Question",{"text":75,"@type":76},"It addresses the performance gap caused by hardware non-idealities such as nonlinearities, device mismatch, and process variations, which degrade accuracy when software-trained parameters are mapped directly to analog neuromorphic hardware.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"Which neuron and synapse models are supported by the proposed framework?",{"text":80,"@type":76},"It supports multiple neuron models including LIF, Hodgkin-Huxley, and Axon-Hillock, and non-volatile analog synapses implemented with floating-gate transistors and ReRAM devices.",{"name":82,"@type":73,"acceptedAnswer":83},"How does hardware-aware training differ from conventional software training in this framework?",{"text":84,"@type":76},"The framework incorporates device-level nonlinearities directly into PyTorch-based training and inference, enabling optimization of physical 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