[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-seo-655970-105":3,"detail-sidebar-cat-0-en-105":81,"doc-detail-655970-en":130},{"code":4,"msg":5,"data":6},0,"ok",{"site_id":7,"language":8,"slug":9,"title":10,"keywords":11,"description":12,"schema_data":13,"social_meta":74,"head_meta":76,"extra_data":78,"updated_unix":80},105,"en","hardware-accelerator-design-automation-lecture-4-control-data-flow-graph","Hardware Accelerator Design & Automation - Lecture 4 - Control Data Flow Graph","","Lecture 4 for ECE 5997 introduces the control data flow graph (CDFG) within an FPGA design workflow using HLS. It outlines the HLS compilation flow, explains intermediate representation purposes such as encoding behavior, enabling analysis and optimization, and supporting retargeting. The session covers control flow analysis concepts including basic blocks, dominance for loop detection, and dataflow analysis using static single assignment (SSA). It further defines basic blocks and the leader rules used to partition a program, illustrated with an example forming basic blocks.",{"@graph":14,"@context":73},[15,34,56],{"@type":16,"itemListElement":17},"BreadcrumbList",[18,23,27,31],{"item":19,"name":20,"@type":21,"position":22},"https://docshare.wps.com","Home","ListItem",1,{"item":24,"name":25,"@type":21,"position":26},"https://docshare.wps.com/document/","Document",2,{"item":28,"name":29,"@type":21,"position":30},"https://docshare.wps.com/document/technology/","Technology",3,{"item":32,"name":10,"@type":21,"position":33},"https://docshare.wps.com/document/hardware-accelerator-design-automation-lecture-4-control-data-flow-graph/655970/",4,{"url":32,"name":10,"@type":35,"image":36,"author":41,"headline":10,"publisher":44,"fileFormat":47,"inLanguage":8,"description":12,"dateModified":48,"datePublished":49,"encodingFormat":47,"isAccessibleForFree":50,"interactionStatistic":51},"DigitalDocument",{"url":37,"@type":38,"width":39,"height":40},"https://docshare.wps.com/thumbnails/hardware-accelerator-design-automation-lecture-4-control-data-flow-graph/655970.png","ImageObject",300,407,{"name":42,"@type":43},"Valentina","Person",{"url":19,"name":45,"@type":46},"DocShare","Organization","application/pdf","2026-11-02","2026-10-25",true,{"@type":52,"interactionType":53,"userInteractionCount":55},"InteractionCounter",{"@type":54},"ViewAction",5,{"@type":57,"mainEntity":58},"FAQPage",[59,65,69],{"name":60,"@type":61,"acceptedAnswer":62},"What is the role of intermediate representation (IR) in HLS?","Question",{"text":63,"@type":64},"The IR encodes program behavior and helps facilitate analysis, optimization, and retargeting.","Answer",{"name":66,"@type":61,"acceptedAnswer":67},"What does control flow analysis determine in a program?",{"text":68,"@type":64},"It determines the control structure of a program and builds control flow graphs (CFGs).",{"name":70,"@type":61,"acceptedAnswer":71},"How are basic blocks formed and what are leader rules?",{"text":72,"@type":64},"A basic block is a consecutive sequence of intermediate statements with control entering only at the start and leaving only at the end. Leaders include the first statement, targets of branch statements, and statements immediately following a branch or return.","https://schema.org",{"og:url":32,"og:type":75,"og:title":10,"og:site_name":45,"og:description":12},"article",{"robots":77,"canonical":32},"index,follow",{"doc_id":79,"site_id":7},655970,1793030257,{"code":4,"msg":82,"data":83},"success",[84,88,92,96,100,104,109,114,119,122,126],{"id":22,"doc_module":4,"doc_module_name":25,"category_name":85,"show_sort_weight":86,"slug":87},"Story & Novel",90,"story-novel",{"id":26,"doc_module":4,"doc_module_name":25,"category_name":89,"show_sort_weight":90,"slug":91},"Literature",80,"literature",{"id":33,"doc_module":4,"doc_module_name":25,"category_name":93,"show_sort_weight":94,"slug":95},"Exam",70,"exam",{"id":55,"doc_module":4,"doc_module_name":25,"category_name":97,"show_sort_weight":98,"slug":99},"Comic",60,"comic",{"id":101,"doc_module":4,"doc_module_name":25,"category_name":29,"show_sort_weight":102,"slug":103},6,50,"technology",{"id":105,"doc_module":4,"doc_module_name":25,"category_name":106,"show_sort_weight":107,"slug":108},7,"Healthcare",40,"healthcare",{"id":110,"doc_module":4,"doc_module_name":25,"category_name":111,"show_sort_weight":112,"slug":113},8,"Research & Report",30,"research-report",{"id":115,"doc_module":4,"doc_module_name":25,"category_name":116,"show_sort_weight":117,"slug":118},9,"Religion & Spirituality",20,"religion-spirituality",{"id":117,"doc_module":4,"doc_module_name":25,"category_name":120,"show_sort_weight":117,"slug":121},"World Cup","world-cup",{"id":123,"doc_module":4,"doc_module_name":25,"category_name":124,"show_sort_weight":123,"slug":125},10,"Lifestyle","lifestyle",{"id":127,"doc_module":4,"doc_module_name":25,"category_name":128,"show_sort_weight":55,"slug":129},19,"General","general",{"code":4,"msg":82,"data":131},{"doc_id":79,"user_id":132,"nickname":42,"user_avatar":133,"doc_module":4,"category_id":101,"category_name":29,"doc_title":10,"doc_description":12,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":55,"is_deleted":4,"is_public":22,"is_downloadable":22,"audit_status":22,"page_count":139,"language":140,"language_code":8,"site_id":7,"html_lang":8,"table_of_contents":141,"faqs":142,"seo_title":143,"seo_description":12,"update_tm":144,"read_time":145},13056703020460,"https://ap-avatar.wpscdn.com/avatar/be000253dac470eee5d?_k=1778207105932848923","ECE 5997  \nHardware Accelerator Design & Automation  \nFall 2021  \nControl Data Flow Graph  \nAnnouncements  \n▸ Lab 2 released (Due Nov 10th)  \nAgenda  \n▸ HLS compilation flow  \n▸ Intermediate representation (IR)  \n– Control data flow graph  \n▸ Control flow analysis  \n– Basic blocks  \n– Dominance relation: Finding loops  \n▸ Dataflow analysis  \n– Static single assignment (SSA)  \nFPGA Design Flow with HLS  \nHLS  \nFlow  \nRTL  \nFlow  \nif (condition) {…  \n} else {  \nt1 = a + b; t2 = c * d; t3 = e + f; t4 = t1 * t2 ; z = t4 – t3 ;  \n}  \nUntimed high-level description  \nTimed design  \nFPGA  \n3  \nIntermediate Representation (IR)  \nSource code  \n▸ Purposes of creating and  \noperating on an IR  \n– Encode the behavior of the program  \nFrontend  \n– Facilitate analysis  \n– Facilitate optimization  \n– Facilitate retargeting  \n▸ The IR we will focus on is control data flow graph (CDFG)  \nAnalysis  \nIR  \nOptimization  \nIR’  \nCode generation  \nTarget code  \nProgram Flow Analysis  \nControl flow analysis  \nFlow analysis ~~ ~~  \nData flow analysis  \nInter-procedural ~~ ~~ Program  \nIntra-procedural ~~ ~~ Function  \nLocal ~~ ~~ Basic block  \n▸ Control flow analysis: determine control structure of a program and build control flow graphs (CFGs)  \n▸ Data flow analysis: determine the flow of data values and build data flow graphs (DFGs)  \nBasic Blocks  \n▸ Basic block: a sequence of consecutive intermediate language statements in which flow of control can only enter at the beginning and leave at the end  \n– Only the last statement of a basic block can be a branch statement and only the first statement of a basic block can be a target of a branch  \nPartitioning a Program into Basic Blocks  \n▸ Each basic block begins with a leader statement  \n▸ Identify leader statements (i.e. , the first statements of basic blocks) by using the following rules:  \n– (i) The first statement in the program is a leader  \n– (ii) Any statement that is the target of a branch statement is a leader (for most intermediate languages these are statements with an associated label)  \n– (iii) Any statement that immediately follows a branch or return statement is a leader  \nExample: Forming the Basic Blocks  \n(1) p = 0  \n(2) i = 1  \n(3) t1 = 4 * i  \n(4) t2 = a[t1]  \n(5) t3 = 4 * i  \n(6) t4 = b[t3]  \n(7) t5 = t2 * t4  \n(8) t6 = p + t5  \n(9) p = t6  \n(10) t7 = i + 1  \n(11) i = t7  \n(12) if i \u003C= 20 goto (3)  \n(13) j = …  \nB2  \nLeader statement is:  \n(1) the first in the program  \n(2) any that is the target of a branch  \n(3) any that immediately follows a branch  \nBasic Blocks:","cbCaijw46J74nkkk","https://ap.wps.com/l/cbCaijw46J74nkkk","pdf",697810,41,"English","# HLS compilation flow\n## Intermediate representation (IR)\n## Control flow analysis\n## Basic blocks\n## Partitioning a program into basic blocks\n## Example: forming basic blocks","[{\"question\":\"What is the role of intermediate representation (IR) in HLS?\",\"answer\":\"The IR encodes program behavior and helps facilitate analysis, optimization, and retargeting.\"},{\"question\":\"What does control flow analysis determine in a program?\",\"answer\":\"It determines the control structure of a program and builds control flow graphs (CFGs).\"},{\"question\":\"How are basic blocks formed and what are leader rules?\",\"answer\":\"A basic block is a consecutive sequence of intermediate statements with control entering only at the start and leaving only at the end. Leaders include the first statement, targets of branch statements, and statements immediately following a branch or return.\"}]","Hardware Accelerator Design & Automation - Lecture 4 - Control Data Flow Graph | PDF",1792965243,103]