[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-32607":3,"doc-seo-32607":27},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"file_id":15,"file_url":16,"file_type":17,"file_size":18,"view_count":4,"is_deleted":4,"is_public":19,"is_downloadable":19,"audit_status":19,"page_count":20,"language":21,"language_code":22,"table_of_contents":23,"faqs":24,"seo_title":13,"seo_description":14,"update_tm":25,"read_time":26},32607,16904993612988,"Olivia Brown","https://ap-avatar.wpscdn.com/davatar_a8503ba1806abce46bf441b54a3ca4cd",8,"Research & Report","Formal Verification of a Dependable State Machine-Based Hardware Architecture for Safety-Critical Cyber-Physical Systems","Increasing reliance on safety-critical cyber-physical systems in domains such as industrial automation, aerospace, and automotive drives demand for dependable, verifiable architectures with fault tolerance. A state-machine-centered formal hardware architecture is presented, structured into analysis, design, implementation, and verification models. NuSMV and waveform-based simulation validate behavior, while LTL/CTL proofs confirm functional and critical properties. A railway interlocking system case study demonstrates correct execution and early fault detection via majority voting, with FPGA synthesis results showing reliability and certification benefits.","cbCaihFGdoXjcdHo","https://ap.wps.com/l/cbCaihFGdoXjcdHo","pdf",6154106,1,15,"English","en","# Abstract\n# Keywords\n# Introduction","[{\"question\":\"What problem does the paper address in safety-critical cyber-physical systems?\",\"answer\":\"It targets the need for verifiable and reliable CPS hardware architectures that support fault tolerance and ensure required safety properties are met.\"},{\"question\":\"How is the proposed architecture organized and validated?\",\"answer\":\"It is divided into analysis, design, implementation, and verification models. The design model is checked with NuSMV, implementation validates requirements using waveform simulations, and verification proves properties using formal temporal logic.\"},{\"question\":\"What case study is used to demonstrate the approach?\",\"answer\":\"A railway interlocking system (RIS) is modeled using temporal logic properties, and a symbolic model verifier (SMV) is used to demonstrate correct execution and fault detection.\"}]",1781738775,38,{"code":4,"msg":28,"data":29},"ok",{"site_id":30,"language":22,"slug":31,"title":13,"keywords":32,"description":14,"schema_data":33,"social_meta":84,"head_meta":86,"extra_data":88,"updated_unix":25},105,"formal-verification-of-a-dependable-state-machine-based-hardware-architecture-for-safety-critical-cyber-physical-systems","",{"@graph":34,"@context":83},[35,52,66],{"@type":36,"itemListElement":37},"BreadcrumbList",[38,42,46,49],{"item":39,"name":40,"@type":41,"position":19},"https://docshare.wps.com","Home","ListItem",{"item":43,"name":44,"@type":41,"position":45},"https://docshare.wps.com/document/","Document",2,{"item":47,"name":12,"@type":41,"position":48},"https://docshare.wps.com/document/research-report/",3,{"item":50,"name":13,"@type":41,"position":51},"https://docshare.wps.com/document/formal-verification-of-a-dependable-state-machine-based-hardware-architecture-for-safety-critical-cyber-physical-systems/32607/",4,{"url":50,"name":13,"@type":53,"author":54,"headline":13,"publisher":56,"fileFormat":59,"description":14,"dateModified":60,"datePublished":60,"encodingFormat":59,"isAccessibleForFree":61,"interactionStatistic":62},"DigitalDocument",{"name":9,"@type":55},"Person",{"url":39,"name":57,"@type":58},"DocShare","Organization","application/pdf","2026-06-17",true,{"@type":63,"interactionType":64,"userInteractionCount":4},"InteractionCounter",{"@type":65},"ViewAction",{"@type":67,"mainEntity":68},"FAQPage",[69,75,79],{"name":70,"@type":71,"acceptedAnswer":72},"What problem does the paper address in safety-critical cyber-physical systems?","Question",{"text":73,"@type":74},"It targets the need for verifiable and reliable CPS hardware architectures that support fault tolerance and ensure required safety properties are met.","Answer",{"name":76,"@type":71,"acceptedAnswer":77},"How is the proposed architecture organized and validated?",{"text":78,"@type":74},"It is divided into analysis, design, implementation, and verification models. The design model is checked with NuSMV, implementation validates requirements using waveform simulations, and verification proves properties using formal temporal logic.",{"name":80,"@type":71,"acceptedAnswer":81},"What case study is used to demonstrate the approach?",{"text":82,"@type":74},"A railway interlocking system (RIS) is modeled using temporal logic properties, and a symbolic model verifier (SMV) is used to demonstrate correct execution and fault detection.","https://schema.org",{"og:url":50,"og:type":85,"og:title":13,"og:site_name":57,"og:description":14},"article",{"robots":87,"canonical":50},"index,follow",{"doc_id":7,"site_id":30}]