[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-81633-en":3,"doc-seo-81633-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":21,"is_downloadable":21,"audit_status":21,"page_count":22,"language":23,"language_code":24,"site_id":25,"html_lang":24,"table_of_contents":26,"faqs":27,"seo_title":13,"seo_description":14,"update_tm":28,"read_time":29},81633,8796095360427,"Lucas Martin","https://ap-avatar.wpscdn.com/davatar_994ba38a5ba835b3df7d355c54d3ed8d",8,"Research & Report","Fast Concurrent Primitives Despite Contention","This document studies how to construct concurrent shared-memory objects when P processes execute in parallel and interact through a memory system that experiences write contention. It presents contention-resolution algorithms that convert hardware primitives prone to write conflicts into contention-tolerant versions. The work builds read/write registers and CAS registers with latency O(log P) with high probability under a relaxed roughly-synchronous stochastic scheduler, even against an adaptive adversary observing full operation history and outcomes, enabling modular composition into larger concurrent designs.","arXiv :2604 . 14530v2 [ cs .DS] 9 Jul 2026  \nFast Concurrent Primitives Despite Contention  \nMichael A. Bender∗ Guy E. Blelloch† Martín Farach-Colton‡ Yang Hu§  \nRob Johnson¶ Rotem Oshman ‖ Renfei Zhou∗∗  \nAbstract  \nWe study the problem of constructing concurrent objects in a setting where P processes run in parallel and interact through a shared memory that is subject to write contention. Our goal is to transform hardware primitives that are subject to write contention into ones that handle contention gracefully.  \nWe give contention-resolution algorithms for several basic primitives, and analyze them under a relaxed, roughly-synchronous stochastic scheduler, where processes run at roughly the same rate up to a constant factor with high probability. Specifically, we construct read/write registers and CAS registers that have latency O(log P) w.h.p. under our scheduler model, using O(1) hardware read/write registers and, in the case of our CAS construction, one hardware CAS register. Our algorithms guarantee performance even when their operations are invoked by an adaptive adversary that is able to see the entire history of operations so far, including their timing and return values. This allows them to be used as building blocks inside larger programs; using this compositionality property, we obtain several other constructions (LL/SC, fetch-and-increment, bounded max registers, and counters) .  \nTo complement our constructions, we give a trade-off showing that even under a perfectly synchronous schedule and even if each process only executes one operation, any algorithm that implements any of the primitives that we consider, uses space M , and has latency at most L with high probability must have expected latency at least Ω(log ML P) .  \n1 Introduction  \nMemory contention is a first-order performance issue in concurrent algorithms and data structures. Contention occurs when multiple processes attempt to modify the same memory location simultaneously: Intoday’s systems, writes to the same memory location are sequentialized by the hardware, meaning that only one request can be served at a time and the others have to wait.  \nSeveral lines of work have tackled the contention problem: in the context of concurrent algorithms,[DHW97 , BHM94 , BM10 , EHS12 , HS03 , ACAH16] consider the stalls model, which charges processes for attempting to access the same memory address at the same time—they each incur a stall, which is counted in the step complexity of the algorithm. This line of work assumes an adversarial worst-case scheduler, and as a result, very strong lower bounds are known even for simple primitives such as fetch-andincrement [DHW97 , EHS12] . In the context of parallel algorithms, the Queue-Read Queue-Write machine model (QRQ W PRAM) [GMR96 , GMR98b, GMR98a] captures contention by queuing accesses to each memory location. Although one variant [GMR98a] assumes an asynchronous model for the purpose of correctness, these works all analyze the performance of their algorithms under a synchronous greedy scheduler, where each process is scheduled as soon as it is ready to take its next step. Other work [BB17] considers a model where instructions are scheduled asynchronously by a worst-case adversarial scheduler, but once an instruc  \ntion starts, it must proceed synchronously, waiting in a queue until prior updates to the same location ∗ Stony Brook University. Email: [bender@cs.stonybrook.edu](bender@cs.stonybrook.edu).  \n†Carnegie Mellon University. Email: [blelloch@cs.cmu.edu](blelloch@cs.cmu.edu).  \n‡New York University. Email: [martin.farach-colton@nyu.edu](martin.farach-colton@nyu.edu).  \n§ Tsinghua University. Email: [y-hu22@mails.tsinghua.edu.cn](y-hu22@mails.tsinghua.edu.cn).  \n¶ VMware Research. Email: [rob@robjohnson.io](rob@robjohnson.io).  \n‖Tel Aviv University and New York University. Email: [roshman@tau.ac.il](roshman@tau.ac.il).  \n∗∗ Carnegie Mellon University. Email: [renfeiz@andrew.cmu.edu](renfeiz@andrew.cmu.edu","cbCaidrgl5HEo2bR","https://ap.wps.com/l/cbCaidrgl5HEo2bR","pdf",1112991,3,1,52,"English","en",105,"# Introduction\n## Overview of Our Scheduler Model","[{\"question\":\"What problem does the document address in concurrent shared-memory systems?\",\"answer\":\"It addresses constructing concurrent objects when multiple processes access shared memory and writes are subject to contention, causing operations to queue or stall at the same location.\"},{\"question\":\"Which synchronization primitives are constructed to handle contention?\",\"answer\":\"The document provides contention-resolution algorithms for basic primitives including read/write registers and compare-and-swap (CAS) registers.\"},{\"question\":\"What latency guarantees are achieved under the proposed scheduler model?\",\"answer\":\"Under a roughly-synchronous stochastic scheduler, the constructed registers achieve latency O(log P) with high probability, while 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