[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-665557-105":59,"doc-detail-665557-en":122},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":115,"head_meta":117,"extra_data":119,"updated_unix":121},105,"en","design-rules-for-nmos-and-cmos-stick-diagrams-layout-diagrams-examples","Design Rules for NMOS and CMOS - Stick Diagrams - Layout Diagrams - Examples","","Design rules for NMOS and CMOS present geometrical specifications that transform an abstract circuit concept into implementable on-chip geometry for silicon fabrication. Layout is defined as the chip top view and the bridge between circuit design and fabrication engineering, while stick diagrams provide symbolic placement and routing information using colored conductive layers. The rules set minimum physical line widths, feature dimensions, and separations, improving area efficiency, yield, and reliability. The material outlines what happens when rules are not followed and introduces layer color codes plus stick-diagram basic rules and steps for transistor labeling.",{"@graph":69,"@context":114},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":30,"@type":76,"position":81},"https://docshare.wps.com/document/technology/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/design-rules-for-nmos-and-cmos-stick-diagrams-layout-diagrams-examples/665557/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/design-rules-for-nmos-and-cmos-stick-diagrams-layout-diagrams-examples/665557.png","ImageObject",300,407,{"name":92,"@type":93},"dbqoiu","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-30","2026-10-29",true,{"@type":102,"interactionType":103,"userInteractionCount":14},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108],{"name":109,"@type":110,"acceptedAnswer":111},"What do the stick-diagram basic rules say about layers and connections?","Question",{"text":112,"@type":113},"Poly (red) over active (green/yellow) forms a FET, while metal lines on different layers can cross without connection. Connections between layers are specified using X (contacts/vias), and transistor placement is represented without exact dimensions.","Answer","https://schema.org",{"og:url":83,"og:type":116,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":118,"canonical":83},"index,follow",{"doc_id":120,"site_id":62},665557,1793304964,{"code":4,"msg":5,"data":123},{"doc_id":120,"user_id":124,"nickname":92,"user_avatar":125,"doc_module":4,"category_id":29,"category_name":30,"doc_title":65,"doc_description":67,"doc_content":126,"file_id":127,"file_url":128,"file_type":129,"file_size":130,"view_count":14,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":131,"language":132,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":133,"faqs":134,"seo_title":135,"seo_description":67,"update_tm":121,"read_time":136},3985747862462,"https://ap-avatar.wpscdn.com/davatar_3d24733baf745e90a7e4bdd5f77d97b2","Design Rules for NMOS  \nand CMOS  \n􀂇 Design Rules  \n􀂇Stick Diagrams  \n􀂇 Layout Diagram  \n􀂇 Examples  \nDarshana Sankhe  \nDesign Rules: Introduction  \n􀂇 Design rules are a set of geometrical specifications that dictate the design of the layout  \n􀂇 Layout is top view of a chip  \n􀂇 Design process are aided by stick diagram and layout  \n􀂇 Stick diagram gives the placement of different components and their connection details  \n􀂇 But the dimensions of devices are not mentioned  \n􀂇 Circuit design with all Drsihana Sankmenhesions is Layout  \nDesign Rules: Introduction  \n􀂇 Fabrication process needs different masks, these masks are prepared from layout  \n􀂇 Layout is an Interface between circuit designer and fabrication engineer  \n􀂇 Layout is made using a set of design rules.  \n􀂇 Design rules allow translation of circuit (usually in stick diagram or symbolic form) into actual geometry in silicon wafer  \n􀂇 These rules usually specify the minimum allowable line widths for physical objects on-chip  \n􀂇  Example: metal, polysilicon, interconnects, diffusion areas, minimum feature dimensions, and minimum allowable separations between two sDrhafSnakhteures.  \nNEED FOR DESIGN RULES  \n􀂇 Better area efficiency  \n􀂇 Better yield  \n􀂇 Better reliability  \n􀂇 Increase the probability of fabricating a successful product on Si wafer  \nIf design rules are not followed:  \n􀂄 Functional or non-functional circuit.  \n􀂄 Design consuming larger Si area.  \n􀂄 The device can fail during or after simulation.  \nDarshana Sankhe  \nColour Codes :  \n\n| Layer | Color | Representation |\n| --- | --- | --- |\n| N+ Active | Green |  |\n| P+ Active | Yellow |  |\n| PolySi | Red |  |\n| Metal 1 | Blue |  |\n| Metal 2 | Magenta |  |\n| Contact | Black | X |\n| Buried contact | Brown | X |\n| Via | Black | X |\n| Implant | Dotted yellow | |\n| N-Well | Dotted Darshana Sankhe Green/Black | |\n\nStick Diagrams :  \n􀂇 A stick diagram is a symbolic representation of a layout.  \n􀂇 In stick diagram, each conductive layer is represented by aline of distinct color.  \n􀂇 Width of line is not important, as stick diagrams just give only wiring and routing information.  \n􀂇 Does show all components/vias, relative placement.  \n􀂇 Does not show exact placement, transistor sizes, wire lengths, wire widths, tub boundaries.  \nDarshana Sankhe  \nStick Diagrams: Basic Rules  \n􀂇 Poly crosses diffusion forms transistor  \n􀂇 Red (poly) over Green(Active), gives a FET.  \nL:W  \n􀂇 Aspect Ratio L:W  \nnFET/ nMOS  \npFET/pMOS  \nDarshana Sankhe  \nStick Diagrams: Basic Rules  \n􀂇 Blue may cross over red or green, without connection.  \n􀂇 Connection between layers is specified with X.  \n􀂇 Metal lines on different layer can cross one another, connections are done using via.  \nDarshana Sankhe  \nStick Diagrams(NMOS): Basic Steps  \n􀂇 Normally, the first step is to draw two parallel metal (blue) V DD and GND rails.  \n􀂇 There should be enough space between them for other circuit elements.  \n􀂇 Next, Active (Green) paths must be drawn for required transistors.  \n􀂇 Do not forget to mark contacts as X, wherever required.  \n􀂇 Remember, Poly (Red) crosses Active (Green/yellow), where transistor is required.  \n􀂇 For depletion mode FET, draw required implants (yellow) .  \n􀂇 Label each transistor with L:W ratio.  \nDarshana Sankhe  \nEnhancement-Mode MOSFET :  \nSource Gate Drain  \n\n|  | n+ ~~ ~~ | \u003Cbr>p\u003Cbr>| n+ |  |\n| --- | --- | --- | --- | --- |\n|  |  |  | bulk Si |  |\n\nPolysilicon SiO2  \n0  \nS ~~ ~~ D  \nDarshana Sankhe","cbCaikpz7mCC3MBF","https://ap.wps.com/l/cbCaikpz7mCC3MBF","pdf",4395495,96,"English","# Design Rules for NMOS and CMOS\n## Design Rules: Introduction\n## Need for Design Rules\n## Colour Codes\n## Stick Diagrams\n## Stick Diagrams: Basic Rules\n## Stick Diagrams (NMOS): Basic Steps\n## Enhancement-Mode MOSFET","[{\"question\":\"What do the stick-diagram basic rules say about layers and connections?\",\"answer\":\"Poly (red) over active (green/yellow) forms a FET, while metal lines on different layers can cross without connection. Connections between layers are specified using X (contacts/vias), and transistor placement is represented without exact dimensions.\"}]","Design Rules for NMOS and CMOS - Stick Diagrams - Layout Diagrams - Examples | PDF",242]