[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-82455-en":3,"doc-seo-82455-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":21,"is_downloadable":21,"audit_status":21,"page_count":22,"language":23,"language_code":24,"site_id":25,"html_lang":24,"table_of_contents":26,"faqs":27,"seo_title":13,"seo_description":14,"update_tm":28,"read_time":29},82455,1099513958607,"Jiven","https://ap-avatar.wpscdn.com/avatar/100002390cf8733938c?x-image-process=image/resize,m_fixed,w_180,h_180&k=1778829742770036399",8,"Research & Report","Comprehensive Verification of Packet Processing","Comprehensive Verification of Packet Processing presents a formal framework to prove end-to-end functional correctness of whole P4-based dataplane behavior on programmable network switches and smart NICs. Existing work verifies only the P4 control block, but packet handling also depends on parsers, deparsers, and non-P4 configurable components such as multicast engines, packet generators, and resubmission paths. The framework specifies and proves correct integration by reasoning that configurable engines are properly configured, validating overall switch behavior via classic P4 applications.","arXiv :2412 . 19908v1 [ cs .PL] 27 Dec 2024  \nComprehensive Verification of Packet Processing  \nSHENGYI WANG, MENGYING PAN, and ANDREW W. APPEL, Princeton University, USA  \nAbstract. To prove the functional correctness of a P4 program running in a programmable network switch or smart NIC, prior works have focused mainly on verifiers for the “control block”(match-action pipeline) . But to verify that a switch handles packets according to a desired specification, proving the control block is not enough. We demonstrate a new comprehensive framework for formally specifying and proving the additional components of the switch that handle each packet: P4 parsers and deparsers, as well as non-P4 components such as multicast engines, packet generators, and resubmission paths. These are generally triggered by having the P4 program set header or metadata fields, which prompt other switch components—fixed-function or configurable—to execute the corresponding actions. Overall behavior is correct only if the “configurable”components are, indeed, configured properly; and we show how to prove that. We demonstrate our framework by verifying the correctness of packet-stream behavior in two classic P4 applications. Our framework is the first to allow the correctness proof of a P4 program to be composed with the correctness proof for these otherswitch components to verify that the switch programming as a whole accomplishes a specified behavior.  \n1 INTRODUCTION  \nHigh-speed network switches (and smart NICs) have many specialized, pipelined, limited-computationdepth components. Some of these components can be programmed in P4, a domain-specific, hardware-independent dataplane programming language for high-speed processing of network packets. P4 is designed to facilitate line-rate, single-pass, pipelined processing of packets through a specialized switch fabric (though P4 can also be compiled to general-purpose CPUs); but this single-pass design naturally comes with significant limitations: P4 does not support general loops, pointer data structures, or even (in some implementations) the ability to access the same data structure more than once during the processing of a packet. The P4 “pipeline” comprises a control block (a.k.a. match-action pipeline) sandwiched between a packet parser and a packet deparser; aswitch might have more than one P4 pipeline, such as an ingress pipeline and an egress pipeline.  \nBecause of the language constraints imposed by the single-pass model, network hardware (switches, NICs, etc.) also has non-P4 components to handle specialized tasks. These components are accessed either inside the control block or before, between, and after P4 pipelines; the P4 program can communicate intentions to those components by setting fields in packet headers or calling\"extern\" functions. These external components—such as packet replicators, packet recirculators, multicast units, packet generators, CPUs and other control-plane units—may be fixed function or they may be configurable. Collectively we refer to them as configurable engines.  \nFigure 1 shows the components ofa Tofino switch. In later sections we will explain their functions; here just note that there are P4-programmable components (purple,“Ingress” and “Egress” rows) and components that are “configurable” but not programmable (grey,“Traffic Manager” row) .  \nIt’s difficult to program and configure these switches, even using an industry-standard language such as P4: the programming model is (necessarily) different than conventional languages for CPU programming, and testing the programs requires setting up a test network with packet generators and high-speed switches. Therefore, formal program verification, to guarantee that a program+configuration serves a specified purpose (or if there is a bug, to catch that bug) can be valuable.  \nIn fact, there are some bugs that simply cannot be found by program testing. In one of our examples, the programmer had forgotten to initialize a ","cbCaioRYfs579YUF","https://ap.wps.com/l/cbCaioRYfs579YUF","pdf",779748,4,1,23,"English","en",105,"# Introduction\n## Problem scope and limitations of P4 single-pass model\n## Role of non-P4 configurable components\n## Motivation for end-to-end formal verification\n## Overall goal and difficulties","[{\"question\":\"Why verifying only the P4 control block is insufficient?\",\"answer\":\"Because correct packet handling depends not only on the match-action pipeline, but also on parsers, deparsers, and non-P4 configurable components triggered by header or metadata changes.\"},{\"question\":\"What additional switch components does the framework cover?\",\"answer\":\"It includes P4 parsers and deparsers, plus configurable engines such as multicast engines, packet generators, and resubmission paths.\"},{\"question\":\"How does the framework ensure overall behavior is correct?\",\"answer\":\"It proves that the configurable components are properly configured and that the composed behavior across P4 and non-P4 parts matches the specified packet-stream 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verifying only the P4 control block is insufficient?","Question",{"text":75,"@type":76},"Because correct packet handling depends not only on the match-action pipeline, but also on parsers, deparsers, and non-P4 configurable components triggered by header or metadata changes.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"What additional switch components does the framework cover?",{"text":80,"@type":76},"It includes P4 parsers and deparsers, plus configurable engines such as multicast engines, packet generators, and resubmission paths.",{"name":82,"@type":73,"acceptedAnswer":83},"How does the framework ensure overall behavior is correct?",{"text":84,"@type":76},"It proves that the configurable components are properly configured and that the composed behavior across P4 and non-P4 parts matches the specified packet-stream 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