[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"detail-sidebar-cat-0-en-105":3,"doc-seo-511412-105":59,"doc-detail-511412-en":130},{"code":4,"msg":5,"data":6},0,"success",[7,13,18,23,28,33,38,43,48,51,55],{"id":8,"doc_module":4,"doc_module_name":9,"category_name":10,"show_sort_weight":11,"slug":12},1,"Document","Story & Novel",90,"story-novel",{"id":14,"doc_module":4,"doc_module_name":9,"category_name":15,"show_sort_weight":16,"slug":17},2,"Literature",80,"literature",{"id":19,"doc_module":4,"doc_module_name":9,"category_name":20,"show_sort_weight":21,"slug":22},4,"Exam",70,"exam",{"id":24,"doc_module":4,"doc_module_name":9,"category_name":25,"show_sort_weight":26,"slug":27},5,"Comic",60,"comic",{"id":29,"doc_module":4,"doc_module_name":9,"category_name":30,"show_sort_weight":31,"slug":32},6,"Technology",50,"technology",{"id":34,"doc_module":4,"doc_module_name":9,"category_name":35,"show_sort_weight":36,"slug":37},7,"Healthcare",40,"healthcare",{"id":39,"doc_module":4,"doc_module_name":9,"category_name":40,"show_sort_weight":41,"slug":42},8,"Research & Report",30,"research-report",{"id":44,"doc_module":4,"doc_module_name":9,"category_name":45,"show_sort_weight":46,"slug":47},9,"Religion & Spirituality",20,"religion-spirituality",{"id":46,"doc_module":4,"doc_module_name":9,"category_name":49,"show_sort_weight":46,"slug":50},"World Cup","world-cup",{"id":52,"doc_module":4,"doc_module_name":9,"category_name":53,"show_sort_weight":52,"slug":54},10,"Lifestyle","lifestyle",{"id":56,"doc_module":4,"doc_module_name":9,"category_name":57,"show_sort_weight":24,"slug":58},19,"General","general",{"code":4,"msg":60,"data":61},"ok",{"site_id":62,"language":63,"slug":64,"title":65,"keywords":66,"description":67,"schema_data":68,"social_meta":123,"head_meta":125,"extra_data":127,"updated_unix":129},105,"en","cmos-vlsi-design-examination-paper-novemberdecember-2018","CMOS VLSI Design Examination Paper - November/December 2018","","This document is an official examination paper for the CMOS VLSI Design course, administered in November/December 2018 for the Electronics Engineering department. The assessment covers fundamental and advanced topics in semiconductor design, including differential amplifier circuit analysis, switched capacitor circuits, operational amplifier design specifications, and source follower stage performance derivations. It also addresses practical engineering concepts such as System on Chip (SoC), System in Package (SiP), PLL non-ideal effects, and MOSFET noise characteristics. The paper provides a structured evaluation of student knowledge across circuit topology, design flows, and noise analysis in mixed-signal integrated circuits.",{"@graph":69,"@context":122},[70,84,105],{"@type":71,"itemListElement":72},"BreadcrumbList",[73,77,79,82],{"item":74,"name":75,"@type":76,"position":8},"https://docshare.wps.com","Home","ListItem",{"item":78,"name":9,"@type":76,"position":14},"https://docshare.wps.com/document/",{"item":80,"name":20,"@type":76,"position":81},"https://docshare.wps.com/document/exam/",3,{"item":83,"name":65,"@type":76,"position":19},"https://docshare.wps.com/document/cmos-vlsi-design-examination-paper-novemberdecember-2018/511412/",{"url":83,"name":65,"@type":85,"image":86,"author":91,"headline":65,"publisher":94,"fileFormat":97,"inLanguage":63,"description":67,"dateModified":98,"datePublished":99,"encodingFormat":97,"isAccessibleForFree":100,"interactionStatistic":101},"DigitalDocument",{"url":87,"@type":88,"width":89,"height":90},"https://docshare.wps.com/thumbnails/cmos-vlsi-design-examination-paper-novemberdecember-2018/511412.png","ImageObject",300,407,{"name":92,"@type":93},"asda1da","Person",{"url":74,"name":95,"@type":96},"DocShare","Organization","application/pdf","2026-10-29","2026-10-06",true,{"@type":102,"interactionType":103,"userInteractionCount":44},"InteractionCounter",{"@type":104},"ViewAction",{"@type":106,"mainEntity":107},"FAQPage",[108,114,118],{"name":109,"@type":110,"acceptedAnswer":111},"What are the primary design specifications for the two-stage operational amplifier mentioned in the exam?","Question",{"text":112,"@type":113},"The design requires a gain (Av) greater than 5000 V/V, a Gain Bandwidth product (GBW) of 5MHz, a phase margin of 60 degrees, a load capacitance (CL) of 10pF, a Slew Rate (SR) greater than 10V/usec, and a power dissipation (Pdiss) of 2mW or less.","Answer",{"name":115,"@type":110,"acceptedAnswer":116},"What topics are covered regarding MOSFET noise in the examination?",{"text":117,"@type":113},"The examination requires students to explain White and Flicker noise in MOSFETs and to derive equations for the output and input-referred noise voltage of a Common Source (CS) amplifier stage.",{"name":119,"@type":110,"acceptedAnswer":120},"What is the requirement for the differential amplifier circuit analysis in Question 1?",{"text":121,"@type":113},"Students are asked to analyze the provided circuit to obtain the voltage gain equation under the condition that transistor M2 is twice as wide as M1, assuming Vin1 equals Vin2.","https://schema.org",{"og:url":83,"og:type":124,"og:title":65,"og:site_name":95,"og:description":67},"article",{"robots":126,"canonical":83},"index,follow",{"doc_id":128,"site_id":62},511412,1791506345,{"code":4,"msg":5,"data":131},{"doc_id":128,"user_id":132,"nickname":92,"user_avatar":133,"doc_module":4,"category_id":19,"category_name":20,"doc_title":65,"doc_description":67,"doc_content":134,"file_id":135,"file_url":136,"file_type":137,"file_size":138,"view_count":44,"is_deleted":4,"is_public":8,"is_downloadable":8,"audit_status":8,"page_count":14,"language":139,"language_code":63,"site_id":62,"html_lang":63,"table_of_contents":140,"faqs":141,"seo_title":142,"seo_description":67,"update_tm":143,"read_time":24,"preview_page_count":4},3985747861852,"https://ap-avatar.wpscdn.com/davatar_155a257f0dc6eb9ab79c44ca47cae57d","o  \nPaper/Subject Code:53001/CMOS VLSI Design  \nSem--ETRX-CBSGS-Nov|Dce.2018之01)i8  \nMax Marks:80  \nTime:3 Hours  \nN.B.1)Question No.1 is compulsory  \n2)Solve any three questions from the remaining questions.  \n3)Assume suitable data if necessary.  \nSolve the following.  \n(a)Analyze following circuit to get voltage gain equation if M2 is twice wide as 5that of M1 and Vin1=Vin2  \n(b)Explain the concept of switched capacitor circuit  \n(c)Compare performance of various op-amp topologies  \n(d)Explain System on Chip and System in Package.  \n(a)Design two stage operational amplifiers that meet the following specifications 20with a phase margin of 60.Assume the channel length is to be lμm,KN’=100μA/V2,KP=20μA/V2,VTN=|VTP|=0.5V,λn=0.06V-1,and λp=  \n0.08V-1 Av>5000v/y,Vdd=2.5V,Vss=-2.5v ,GBW=5MHz,CL=10pf,SR>10vusec,Vout range=+/-2V,ICMR=-1 to 2V,Pdiss≤2mw..  \n?3 (a)Derive expression for voltage gain AV and output resistance Ro of source 10follower stage.  \n(b)Compare full custom and semi-custom design in terms of its trade-off and 5applications.  \n5  \n(C)Explain Non-ideal effects in PLL.  \n4 a)Derive equation of dfferential gain,common mode gain and CMRR of 10differential amplifier.  \n(b)Explain White &Flicker noise in MOSFET.Derive equation for output and 10input referred noise voltage of CS stage  \n5 (a)Draw and explain AMS design flow.10  \n(b)Draw and explain discrete time integrator along with the output waveform.   10","cbCaijWSpAYwlRej","https://ap.wps.com/l/cbCaijWSpAYwlRej","pdf",1994239,"English","# CMOS VLSI Design Examination Paper\n## Circuit Analysis and Design Problems\n## Theoretical Concepts and Comparisons\n## Noise Analysis and System Design","[{\"question\":\"What are the primary design specifications for the two-stage operational amplifier mentioned in the exam?\",\"answer\":\"The design requires a gain (Av) greater than 5000 V/V, a Gain Bandwidth product (GBW) of 5MHz, a phase margin of 60 degrees, a load capacitance (CL) of 10pF, a Slew Rate (SR) greater than 10V/usec, and a power dissipation (Pdiss) of 2mW or less.\"},{\"question\":\"What topics are covered regarding MOSFET noise in the examination?\",\"answer\":\"The examination requires students to explain White and Flicker noise in MOSFETs and to derive equations for the output and input-referred noise voltage of a Common Source (CS) amplifier stage.\"},{\"question\":\"What is the requirement for the differential amplifier circuit analysis in Question 1?\",\"answer\":\"Students are asked to analyze the provided circuit to obtain the voltage gain equation under the condition that transistor M2 is twice as wide as M1, assuming Vin1 equals Vin2.\"}]","CMOS VLSI Design Examination Paper - November/December 2018 | PDF",1791251634]