[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-86411-en":3,"doc-seo-86411-105":29,"detail-sidebar-cat-0-en-105":90},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":21,"is_downloadable":21,"audit_status":21,"page_count":11,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":13,"seo_description":14,"update_tm":27,"read_time":28},86411,3848291630094,"Emma Wilson","https://eur-avatar.wpscdn.com/davatar_085a072bc5b1113ac321206ff7593b45",8,"Research & Report","CMAX-CAMEL Coarse to Fine Adaptive Memory Efficient Low Power Edge Processor for Contrast Maximization","Contrast maximization (CMAX) provides a geometric approach to event-based motion estimation, yet its iterative warp-and-accumulate pipeline causes input-dependent computation and frequent memory traffic, making real-time, low-power edge deployment difficult. CMAX-CAMEL introduces a coarse-to-fine adaptive, memory-centric processor that adjusts execution stages based on observed event distribution. Banked parallel memory maintains throughput, while subsampling-coupled accumulation reduces memory accesses. FPGA results at 200 MHz show up to 19% higher accuracy, 53.3% lower latency, 42% fewer effective memory accesses, and 52.2% less system energy including adaptation overhead.","CMAX-CAMEL: A Coarse-to-Fine Adaptive, Memory-Efficient, and Low-Power Edge Processor for Contrast Maximization  \nKyeongpil Min, Jongin Choi, Kyeongwon Lee, and Woojoo Lee  \narXiv :2605 .24017v2 [ cs .AR] 11 Jul 2026  \nAbstract  \nContrast maximization (CMAX) is a direct geometric framework for event-based motion estimation, but its iterative warp-and-accumulate pipeline incurs input-dependent computation and frequent memory accesses, challenging real-time, low-power edge deployment. We present CMAX-CAMEL, a coarse-to-fine adaptive, memoryefficient, low-power edge processor for CMAX. CMAX-CAMEL combines a runtime-adaptive execution strategy with a memorycentric processor architecture. It adjusts coarse-to-fine execution according to the observed event distribution, prioritizing stages likely to improve estimation accuracy while suppressing low-value iterations and unnecessary stage transitions. Architecturally, a banked parallel memory organization sustains real-time throughput while reducing latency, and a subsampling-coupled accumulation structure lowers memory-access activity along the warp-andaccumulate dataflow. On a Virtex FPGA prototype operating at 200 MHz, CMAX-CAMEL improves estimation accuracy by up to 19% over fixed coarse-to-fine schedules, reduces processing latency by 53.3%, lowers effective memory accesses by 42%, and cuts total system energy by 52.2%, including adaptation overheads. These results show that CMAX-CAMEL is an HW–SW co-design that co-optimizes execution policy and data movement for real-time, low-power event-based motion estimation at the edge.  \n1 Introduction  \nAutonomous and mobile edge systems require motion estimation that remains reliable under fast motion, abrupt illumination changes, and stringent energy and latency constraints [1, 2] This capability is a fundamental front-end component of visual SLAM and odometry, where the ego-motion of a camera must be inferred from sequential observations [3, 4] . Event cameras, especially Dynamic Vision Sensors (DVS) [5], are well suited to this setting because they asynchronously report local brightness changes [6–8] . They offer microsecond-level temporal resolution and wide dynamic range for handling fast motion and challenging lighting, while generating sparse outputs that reduce data movement [9, 10] . Under the resource and power constraints of edge deployment, however, pure event-based pipelines remain particularly attractive because they operate directly on the event stream without relying on auxiliary sensing modalities or power-hungry inference [11–13] . Within this  \nThis paper has been accepted for publication in the Proceedings of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2026 .  \nThis work was supported in part by the National Research Foundation of Korea (NRF) grant funded by MSIT (No. RS-2024-00345668), and in part by Institute of Information & communications Technology Planning & Evaluation (IITP) grants funded by MSIT (No. RS-2023-00277060) .  \nKyeongpil Min and Jongin Choi contributed equally to this work.  \nWoojoo Lee is the corresponding author.  \nISLPED’26, Evanston, Illinois, USA 2026.  \nclass of methods, contrast maximization (CMAX) [14], which estimates motion by warping events to maximize the contrast of an accumulated event image, has emerged as a representative geometric framework and has been extended to rotational motion estimation, SLAM, and motion segmentation [15–21] . Yet, despite substantial algorithmic progress, processor-and system-level support needed to make CMAX a practical real-time, low-power primitive for edge platforms remains limited.  \nRecent efforts have explored both coarse-to-fine execution and hardware acceleration for CMAX [22, 23] . Collectively, these studies suggest two key design opportunities: the utility of CMAX computation is highly non-uniform across stages and iterations, and the repeated warp-and-accumulate dataflow can benefit substantially from dedic","cbCaipW0YjRBpji0","https://ap.wps.com/l/cbCaipW0YjRBpji0","pdf",3920787,4,1,"English","en",105,"# Introduction\n## Event-based motion estimation and CMAX\n## Coarse-to-fine execution and hardware acceleration\n## CMAX-CAMEL contributions","[{\"question\":\"What problem does CMAX-CAMEL target in contrast maximization pipelines?\",\"answer\":\"CMAX-CAMEL targets input-dependent computation and frequent memory accesses in the iterative warp-and-accumulate process, which hinder real-time, low-power execution on edge devices.\"},{\"question\":\"How does CMAX-CAMEL adapt coarse-to-fine execution?\",\"answer\":\"It dynamically adjusts execution stages according to the observed event distribution, prioritizing stages likely to improve estimation accuracy while suppressing low-value iterations and unnecessary transitions.\"},{\"question\":\"What architectural techniques reduce latency and memory-access activity?\",\"answer\":\"CMAX-CAMEL uses a banked parallel memory organization for sustained real-time throughput and a subsampling-coupled accumulation structure to lower memory-access activity along the warp-and-accumulate dataflow.\"}]",1784211573,20,{"code":4,"msg":30,"data":31},"ok",{"site_id":24,"language":23,"slug":32,"title":13,"keywords":33,"description":14,"schema_data":34,"social_meta":85,"head_meta":87,"extra_data":89,"updated_unix":27},"cmax-camel-coarse-to-fine-adaptive-memory-efficient-low-power-edge-processor-for-contrast-maximization","",{"@graph":35,"@context":84},[36,52,67],{"@type":37,"itemListElement":38},"BreadcrumbList",[39,43,47,50],{"item":40,"name":41,"@type":42,"position":21},"https://docshare.wps.com","Home","ListItem",{"item":44,"name":45,"@type":42,"position":46},"https://docshare.wps.com/document/","Document",2,{"item":48,"name":12,"@type":42,"position":49},"https://docshare.wps.com/document/research-report/",3,{"item":51,"name":13,"@type":42,"position":20},"https://docshare.wps.com/document/cmax-camel-coarse-to-fine-adaptive-memory-efficient-low-power-edge-processor-for-contrast-maximization/86411/",{"url":51,"name":13,"@type":53,"author":54,"headline":13,"publisher":56,"fileFormat":59,"inLanguage":23,"description":14,"dateModified":60,"datePublished":61,"encodingFormat":59,"isAccessibleForFree":62,"interactionStatistic":63},"DigitalDocument",{"name":9,"@type":55},"Person",{"url":40,"name":57,"@type":58},"DocShare","Organization","application/pdf","2026-07-28","2026-07-16",true,{"@type":64,"interactionType":65,"userInteractionCount":20},"InteractionCounter",{"@type":66},"ViewAction",{"@type":68,"mainEntity":69},"FAQPage",[70,76,80],{"name":71,"@type":72,"acceptedAnswer":73},"What problem does CMAX-CAMEL target in contrast maximization pipelines?","Question",{"text":74,"@type":75},"CMAX-CAMEL targets input-dependent computation and frequent memory accesses in the iterative warp-and-accumulate process, which hinder real-time, low-power execution on edge devices.","Answer",{"name":77,"@type":72,"acceptedAnswer":78},"How does CMAX-CAMEL adapt coarse-to-fine execution?",{"text":79,"@type":75},"It dynamically adjusts execution stages according to the observed event distribution, prioritizing stages likely to improve estimation accuracy while suppressing low-value iterations and unnecessary transitions.",{"name":81,"@type":72,"acceptedAnswer":82},"What architectural techniques reduce latency and memory-access activity?",{"text":83,"@type":75},"CMAX-CAMEL uses a banked parallel memory organization for sustained real-time throughput and a subsampling-coupled accumulation structure to lower memory-access activity along the warp-and-accumulate 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