[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-82009-en":3,"doc-seo-82009-105":29,"detail-sidebar-cat-0-en-105":90},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":13,"seo_description":14,"update_tm":27,"read_time":28},82009,687197207639,"Asher","https://ap-avatar.wpscdn.com/davatar_a8503ba1806abce46bf441b54a3ca4cd",8,"Research & Report","ATLAS: Automated HLS for DL-Optimized FPGAs","FPGA architectures increasingly embed domain-specific in-fabric hardblocks to accelerate deep learning inference, especially GEMM, yet extracting performance requires manual RTL expertise: microarchitecture understanding, RTL instantiation, and careful tiling/control. While C/C++-based HLS improves productivity, native support for generating custom hardblocks is lacking and prior blackbox methods remain layer-by-layer manual. ATLAS delivers an end-to-end automated flow from a high-level DL model to FPGA hardware using GEMM as a universal abstraction and architecture-aware hardblock RTL generation, reducing design effort while preserving efficiency.","ATLAS: Automated HLS for DL-Optimized FPGAs  \nRuthwik Reddy Sunketa  \nArizona State University Tempe, AZ, USA[rsunketa@asu.edu](rsunketa@asu.edu)  \nAman Arora  \nArizona State University Tempe, AZ, USA [aman.kbm@asu.edu](aman.kbm@asu.edu)  \narXiv :2607 .07643v 1 [ cs .AR] 8 Jul 2026  \nAbstract—FPGA architectures increasingly incorporate domain-specific in-fabric hardblocks to accelerate Deep Learning (DL) inference, particularly General Matrix Multiplication (GEMM), which dominates DL computation. To realize the performance gains of these hardblocks, manual RTL design is required: the programmer must understand the hardblock microarchitecture, instantiate them in RTL, and manage tiling and control logic. While programming in C/C++ and using HLS tools has increased the abstraction level and productivity of FPGA engineers, HLS tools do not support code generation for custom hardblocks natively. Prior work has demonstrated that blackbox mechanisms in HLS tools can be used to target custom hardblocks, but this still requires explicit function calls in user-written HLS C and manual creation of RTL IP libraries, significant effort that must be repeated for every layer in a DL model. Furthermore, for DL, an even high-level programming interface, e.g., Pytorch/Keras instead of C/C++, is desirable for improved programmability and user adoption.  \nWe present ATLAS, a fully automated flow from a high-level DL model description to a hardware implementation on an FPGA with custom in-fabric DL-optimized hardblocks, requiring no manual RTL design or explicit hardblock instantiation from the end user. Our approach uses GEMM as a universal abstraction layer and comprises two components: (1) hls4ml-GEMM, a compiler frontend that transforms DL layers into HLS C code with architecture-agnostic GEMM function calls, and (2) a GEMM IP Generator, an architecture-aware backend that produces hardblock-based RTL wrappers with tiling logic, control FSMs, and scheduling metadata. We evaluate the flow across 11 DL designs, including individual fully connected, convolution, and attention layers, as well as full CNN, MLP, and Transformer models targeting an FPGA architecture with Tensor Slices using Catapult for HLS and VTR for implementation. Results demonstrate that, on the layer-wise designs, our automated flow reaches compute–area efficiency approaching that of a handwritten RTL baseline (approximately 89%) while exceeding the soft-logic hls4ml baseline by 24% . On the full designs, it attainsa geomean efficiency of approximately 63% of the RTL baseline and approximately 42% above the soft-logic hls4ml baseline, reducing design time from days to hours.  \nI. INTRODUCTION  \nFPGA architectures increasingly include domain-specific infabric hardblocks to accelerate Deep Learning (DL) inference. These hardblocks typically target matrix multiplication, the computational bottleneck in DL workloads, and provide significant performance and energy efficiency improvements for DL applications over soft-logic 1 implementations. Examples  \n1In this paper, we refer to CLBs, DSPs, and BRAMs as soft-logic, and specialized in-fabric DL compute blocks as hardblocks.  \nBaseline  \nProposed  \n|  |\n| --- |\n|  |\n|  DL-Optimized FPGA  |\n|  |\n\nCLB  BRAM  DSP  DL hardblocks  \nFig. 1: On a DL-optimized FPGA, the baseline hls4ml flow (left) maps DL workloads only onto soft-logic resources, leaving the specialized hardblocks unused. The proposed ATLAS flow (right) enables automatic mapping onto the DL hardblocks.  \ninclude Intel AI Tensor Blocks [1], Tensor Slices [2], and the Analog Dot Product Engines of AzureLily [3] .  \nProgramming these hardblocks requires RTL expertise. The end-user must understand the hardblock microarchitecture, tile computations to match its fixed dimensions, write Verilog designs with control FSMs, and manage data movement. This effort must be repeated for every layer in a network, making end-to-end implementation of a full DL model labor-intensive and error-","cbCairmrIk40AIIN","https://ap.wps.com/l/cbCairmrIk40AIIN","pdf",1040798,1,9,"English","en",105,"# Introduction\n## FPGA hardblocks and DL mapping challenges\n## Limitations of existing HLS and prior blackbox methods\n## Overview of ATLAS and the GEMM abstraction","[{\"question\":\"Why do DL-optimized FPGA hardblocks require manual RTL design today?\",\"answer\":\"Mapping to hardblocks typically needs RTL expertise: users must understand microarchitecture details, tile computations to fixed dimensions, write Verilog control FSMs, and manage data movement for each layer.\"},{\"question\":\"What problem does ATLAS address compared with existing HLS flows?\",\"answer\":\"ATLAS automates end-to-end compilation to custom in-fabric hardblocks. It avoids explicit hardblock instantiation and repeated manual RTL/IP creation for every DL layer.\"},{\"question\":\"How does ATLAS connect a high-level DL model to DL-optimized hardblocks?\",\"answer\":\"ATLAS uses GEMM as a universal abstraction layer: an architecture-agnostic frontend emits HLS C with architecture-agnostic GEMM calls, while an architecture-aware backend generates hardblock-based RTL wrappers with tiling logic, control FSMs, and scheduling metadata.\"}]",1784177547,23,{"code":4,"msg":30,"data":31},"ok",{"site_id":24,"language":23,"slug":32,"title":13,"keywords":33,"description":14,"schema_data":34,"social_meta":85,"head_meta":87,"extra_data":89,"updated_unix":27},"atlas-automated-hls-for-dl-optimized-fpgas","",{"@graph":35,"@context":84},[36,53,67],{"@type":37,"itemListElement":38},"BreadcrumbList",[39,43,47,50],{"item":40,"name":41,"@type":42,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":44,"name":45,"@type":42,"position":46},"https://docshare.wps.com/document/","Document",2,{"item":48,"name":12,"@type":42,"position":49},"https://docshare.wps.com/document/research-report/",3,{"item":51,"name":13,"@type":42,"position":52},"https://docshare.wps.com/document/atlas-automated-hls-for-dl-optimized-fpgas/82009/",4,{"url":51,"name":13,"@type":54,"author":55,"headline":13,"publisher":57,"fileFormat":60,"inLanguage":23,"description":14,"dateModified":61,"datePublished":61,"encodingFormat":60,"isAccessibleForFree":62,"interactionStatistic":63},"DigitalDocument",{"name":9,"@type":56},"Person",{"url":40,"name":58,"@type":59},"DocShare","Organization","application/pdf","2026-07-16",true,{"@type":64,"interactionType":65,"userInteractionCount":4},"InteractionCounter",{"@type":66},"ViewAction",{"@type":68,"mainEntity":69},"FAQPage",[70,76,80],{"name":71,"@type":72,"acceptedAnswer":73},"Why do DL-optimized FPGA hardblocks require manual RTL design today?","Question",{"text":74,"@type":75},"Mapping to hardblocks typically needs RTL expertise: users must understand microarchitecture details, tile computations to fixed dimensions, write Verilog control FSMs, and manage data movement for each layer.","Answer",{"name":77,"@type":72,"acceptedAnswer":78},"What problem does ATLAS address compared with existing HLS flows?",{"text":79,"@type":75},"ATLAS automates end-to-end compilation to custom in-fabric hardblocks. It avoids explicit hardblock instantiation and repeated manual RTL/IP creation for every DL layer.",{"name":81,"@type":72,"acceptedAnswer":82},"How does ATLAS connect a high-level DL model to DL-optimized hardblocks?",{"text":83,"@type":75},"ATLAS uses GEMM as a universal abstraction layer: an architecture-agnostic frontend emits HLS C with architecture-agnostic GEMM calls, while an architecture-aware backend generates hardblock-based RTL wrappers with tiling logic, control FSMs, and scheduling metadata.","https://schema.org",{"og:url":51,"og:type":86,"og:title":13,"og:site_name":58,"og:description":14},"article",{"robots":88,"canonical":51},"index,follow",{"doc_id":7,"site_id":24},{"code":4,"msg":5,"data":91},[92,96,100,104,109,114,119,122,126,129,133],{"id":20,"doc_module":4,"doc_module_name":45,"category_name":93,"show_sort_weight":94,"slug":95},"Story & Novel",90,"story-novel",{"id":46,"doc_module":4,"doc_module_name":45,"category_name":97,"show_sort_weight":98,"slug":99},"Literature",80,"literature",{"id":52,"doc_module":4,"doc_module_name":45,"category_name":101,"show_sort_weight":102,"slug":103},"Exam",70,"exam",{"id":105,"doc_module":4,"doc_module_name":45,"category_name":106,"show_sort_weight":107,"slug":108},5,"Comic",60,"comic",{"id":110,"doc_module":4,"doc_module_name":45,"category_name":111,"show_sort_weight":112,"slug":113},6,"Technology",50,"technology",{"id":115,"doc_module":4,"doc_module_name":45,"category_name":116,"show_sort_weight":117,"slug":118},7,"Healthcare",40,"healthcare",{"id":11,"doc_module":4,"doc_module_name":45,"category_name":12,"show_sort_weight":120,"slug":121},30,"research-report",{"id":21,"doc_module":4,"doc_module_name":45,"category_name":123,"show_sort_weight":124,"slug":125},"Religion & Spirituality",20,"religion-spirituality",{"id":124,"doc_module":4,"doc_module_name":45,"category_name":127,"show_sort_weight":124,"slug":128},"World Cup","world-cup",{"id":130,"doc_module":4,"doc_module_name":45,"category_name":131,"show_sort_weight":130,"slug":132},10,"Lifestyle","lifestyle",{"id":134,"doc_module":4,"doc_module_name":45,"category_name":135,"show_sort_weight":105,"slug":136},19,"General","general"]