[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-120467-en":3,"doc-seo-120467-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":4,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},120467,962075114101,"Seraphina","https://ap-avatar.wpscdn.com/avatar/e000253a75eb197efd?x-image-process=image/resize,m_fixed,w_180,h_180&k=1780044092746381165",8,"Research & Report","Assessing RISC-V Vector Extension for Machine Learning","Report presents a partial design and implementation of a soft RISC-V vector extension on an FPGA, following the ratified v1.0 specification, to evaluate suitability for machine learning. Performance results come from a matrix multiplication benchmarking program built with GCC, while prototype behavior is altered via configurable vector length and execute-stage forwarding. Resource use, power consumption, and timing are estimated using Vivado synthesis. Results show up to 5.4x relative improvement over scalar RISC-V, balanced by higher resource and power costs.","Assessing RISC-V Vector Extension for Machine Learning  \nMaster’s thesis in Embedded Electronic System Design  \nJohan Hellström and Marwan Ghamlouch  \nDepartment of Computer Science and Engineering CHALMERS UNIVERSITY OF TECHNOLOGY UNIVERSITY OF GOTHENBURG  \nGothenburg, Sweden 2023  \nMaster’s thesis 2023  \nAssessing RISC-V Vector Extension for Machine Learning  \nJohan Hellström and Marwan Ghamlouch  \nDepartment of omputer Science and Engineering Chalmers University of Technology University of Gothenburg Gothenburg, Sweden 2023  \nAssessing RISC-V Vector Extension for Machine Learning Johan Hellström and Marwan Ghamlouch  \n© Johan Hellström and Marwan Ghamlouch, 2023 .  \nSupervisor: Per Larsson-Edefors, CSE  \nAdvisors: Göran Bilski & Tryggve Mathiesen, AMD  \nExaminer: Lena Peterson, CSE  \nMaster’s Thesis 2023  \nDepartment of Computer Science and Engineering  \nChalmers University of Technology and University of Gothenburg SE-412 96 Gothenburg  \nTelephone +46 31 772 1000  \nCover: AI generated image of an FPGA circuit board  \nTypeset in LATEX  \nGothenburg, Sweden 2023  \nAssessing RISC-V Vector Extension for Machine Learning Johan Hellström and Marwan Ghamlouch  \nDepartment of Computer Science and Engineering  \nChalmers University of Technology and University of Gothenburg  \nAbstract  \nThis report presents a partial design and implementation of a soft RISC-V vector extension on a field-programmable gate array (FPGA) based on the most recent and ratified specification (v1.0), with the aim to investigate the suitability of RISC-V vector processor extensions for machine learning applications.  \nThe results were obtained by creating a matrix multiplication benchmarking program compiled in GCC and modifying configurations that altered the behavior of the designed prototype. The configurations that could be altered were vector length and whether or not forwarding from the execute stage was enabled. We also implemented our design in a synthesis tool (Vivado) in order to estimate resource usage, power consumption and timing.  \nFrom our prototype we were able to find that we could, for our benchmarking program, improve the performance by up to 5.4 relative to a scalar RISC-V processor, but at the cost of a notable resource usage and power increase.  \nIn conclusion, we believe that vector extension is suitable for machine learning applications because of the achievable performance increase, however the design should be heavily optimized to reduce the resource utilization to capitalize on this.  \nKeywords: RISC-V, ISA, ISA extension, vector, processor, machine learning.  \nAcknowledgments  \nThis thesis was a huge undertaking that could not have been done without the continuous and thorough support of others. We can not thank enough our academic supervisor Per Larsson-Edefors for helping us set and maintain realistic ambitions through out our work, and our industry supervisors Göran Bilski and Tryggve Mathiesen (and the AMD office at large!) for providing invaluable technical guidance every step of the way to accomplish this thesis.  \nMarwan would like to extend his gratitude to his family for being a great source of inspiration for what can be achieved in life, and for all the work and effort they spent to help me be in a position to take on this opportunity. He would like to also thank his Olof friends for their continuous support, and his best friend for always being by his side and supporting him through this journey.  \nJohan would like to also thank his family and friends for helping him with various issues and pushing him to achieve his goals. He would also like to thank them forgiving feedback on several aspects of the thesis.  \nJohan Hellström and Marwan Ghamlouch, Gothenburg, 2023-06-26  \nContents  \nGlossary xi  \n1 Introduction 1  \n1.1 Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  \n1.2 Gap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  \n1.3 Problem Statement . . . . . . . . . .","cbCairLnRd7GgNqn","https://ap.wps.com/l/cbCairLnRd7GgNqn","pdf",2012140,1,60,"English","en",105,"# Glossary\n# Introduction\n## Background\n## Gap\n## Problem Statement\n## Limitations\n## Thesis Outline\n# Theory\n## Field-Programmable Gate Arrays (FPGAs)\n## Vector Instructions\n## Machine Learning\n## Digital Signal Processing\n## Multiplication in Hardware\n## Pipeline Hazards\n## Processor Performance Metrics\n# Methods\n## Overview\n## Materials\n## Benchmarks\n## Testbench\n# Prototype\n## Overview","[{\"question\":\"What is the goal of this thesis on the RISC-V vector extension?\",\"answer\":\"The thesis evaluates whether RISC-V vector processor extensions are suitable for machine learning workloads by designing and implementing a soft vector extension on an FPGA.\"},{\"question\":\"How were performance results obtained?\",\"answer\":\"A matrix multiplication benchmarking program compiled in GCC was used, and the prototype was configured by changing vector length and toggling execute-stage forwarding.\"},{\"question\":\"What trade-off does the prototype show compared with a scalar RISC-V processor?\",\"answer\":\"The design can improve performance by up to 5.4 relative to scalar RISC-V, but it does so with a notable increase in resource usage and power.\"}]","Assessing RISC-V Vector Extension for Machine Learning | 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is the goal of this thesis on the RISC-V vector extension?","Question",{"text":75,"@type":76},"The thesis evaluates whether RISC-V vector processor extensions are suitable for machine learning workloads by designing and implementing a soft vector extension on an FPGA.","Answer",{"name":78,"@type":73,"acceptedAnswer":79},"How were performance results obtained?",{"text":80,"@type":76},"A matrix multiplication benchmarking program compiled in GCC was used, and the prototype was configured by changing vector length and toggling execute-stage forwarding.",{"name":82,"@type":73,"acceptedAnswer":83},"What trade-off does the prototype show compared with a scalar RISC-V processor?",{"text":84,"@type":76},"The design can improve performance by up to 5.4 relative to scalar RISC-V, but it does so with a notable increase in resource usage and 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