[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-121587-en":3,"doc-seo-121587-105":30,"detail-sidebar-cat-0-en-105":91},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},121587,13056703020460,"Valentina","https://ap-avatar.wpscdn.com/avatar/be000253dac470eee5d?_k=1778207105932848923",8,"Research & Report","A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration - Research highlights","Time-to-digital converters (TDCs) implemented on FPGA face major precision obstacles: FPGA delay elements vary due to process and routing differences, creating non-uniform time measurement that typically demands extensive calibration. In addition, analog-oriented time extraction must be adapted to FPGA’s digital fabric, adding further design complexity. This work proposes an ML-aided self-calibration strategy combining custom placement and routing optimization with machine learning correction models, evaluating three ML models to map raw TDC outputs to corrected timing values. Results on a Kintex UltraScale FPGA achieve timing precision below 15 ps, improving conventional encoder-based FPGA TDCs by over 10.5× and reaching ASIC-level performance.","POLITECNICO DI TORINO  \nRepository ISTITUZIONALE  \nA novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration  \nOriginal  \nA novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration / Amini Bardpareh, Arash; Vacca, Eleonora; Nicolini, Davide; De Sio, Corrado; Azimi, Sarah; Sterpone, Luca; Fiorina, Elisa; Data, Emanuele Maria; Mas Milian, Felix. -In: INTELLIGENT SYSTEMS WITH APPLICATIONS. -ISSN 2667-3053. -30:(2026) .[10.1016/j.iswa.2026.200644]  \nAvailability:  \nThis version is available at: 11583/3008177 since: 2026-03-04T12:20:29Z  \nPublisher: Elsevier  \nPublished  \nDOI:10.1016/j.iswa.2026.200644  \nTerms of use:  \nThis article is made available under terms and conditions as specified in the corresponding bibliographic description in the repository  \nPublisher copyright  \n(Article begins on next page)  \n26 March 2026  \nIntelligent Systems with Applications 30 (2026) 200644  \nContents lists available at ScienceDirect  \nIntelligent Systems with Applications  \njournal [homepage: www.journals.elsevier.com/intelligent-systems-with-applications](homepage: www.journals.elsevier.com/intelligent-systems-with-applications)  \n| A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration\u003Cbr>Arash Amini Bardpareha,* , Eleonora Vacca a , Davide Nicolinia , Corrado De Sioa , Sarah Azimia , Luca Sterponea , Elisa Fiorinab , Emanuele Maria Data b ,\u003Cbr>Felix Mas Milian b \u003Cbr>a Dipartimento di Automatica e Informatica, Politecnico di Torino, Torino, Italy b Istituto Nazionale di Fisica Nucleare, Torino, Italy |  |  |\n| --- | --- | --- |\n| A R T I C L E I N F O |  | A B S T R A C T |\n| Keywords:\u003Cbr>FPGA\u003Cbr>Machine learning Neural network\u003Cbr>Time-to-digital converter |  | Time-to-digital converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) encounter significant challenges in achieving high precision. Unlike Application-Specific Integrated Circuits, FPGA-based TDCs must depend on standard logic elements as delay units, with each contributing different propagation delays due to process variations and available routing resources. These inconsistencies introduce non-uniformities in time measurement, degrading accuracy and thus requiring extensive calibration. A second major challenge is adapting analog-based time measurement techniques to the inherently digital nature ofFPGAs. This work proposes a novel approach that eliminates the lengthy, time-consuming manual calibration by combining placement and routing optimization with machine learning techniques. We propose an approach based on custom placement and routing to minimize disturbance, while remaining errors due to process variation are compensated exploiting machine learning-based correction models. The work proposes and evaluates three different Machine-Learning (ML) models to interpret raw TDC outputs. Exploiting ML, we achieve a high-precision time measurement system capable of addressing the disturbances and non-linearities intrinsic to FPGA-based TDCs. This approach significantly reduces design complexity, accelerates deployment, and enhances the precision of FPGA-based TDCs, making them more scalable and suitable for a broad range of applications. Experimental results on a Kintex UltraScale FPGA show that the proposed ML-aided TDC achieves a timing precision below 15 ps, improving the precision of a conventional encoder-based FPGA TDC by more than 10.5 × and reaching performance comparable to a state-of-the-art ASIC TDC. |\n\n1. Introduction  \nTime-to-digital converters (TDCs) measure the time interval between two events by converting timing information into a digital value. They are widely used in applications such as LiDAR (Genschow, 2015), medical imaging (Garzetti et al., 2019), particle physics (Roy et al., 2017), and high-speed communication (Zhang et al., 2012), where high-resolution time measurement is critical. Traditionally, TDCs are implemented using Applica","cbCaioWNLgXO7kSn","https://ap.wps.com/l/cbCaioWNLgXO7kSn","pdf",3091811,1,15,"English","en",105,"# Abstract\n# Introduction\n# Background and challenges of FPGA-based TDCs\n## Tapped Delay Line architecture\n## Calibration burden and non-uniformities","[{\"question\":\"Why do FPGA-based TDCs require extensive calibration?\",\"answer\":\"Because FPGA delay elements exhibit propagation-delay variations driven by process differences and routing resources, leading to non-uniformities in measured time.\"},{\"question\":\"How does the proposed method reduce manual calibration effort?\",\"answer\":\"It combines placement and routing optimization to minimize disturbance with machine learning-based correction models that compensate remaining errors.\"},{\"question\":\"What performance results are reported for the ML-aided TDC?\",\"answer\":\"On a Kintex UltraScale FPGA, the system achieves timing precision below 15 ps, improving an encoder-based FPGA TDC by more than 10.5× and approaching state-of-the-art ASIC performance.\"}]","A novel FPGA-based time-to-digital converter featuring machine learning-aided self-calibration - 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