[{"data":1,"prerenderedAt":-1},["ShallowReactive",2],{"doc-detail-127258-en":3,"doc-seo-127258-105":30,"detail-sidebar-cat-0-en-105":92},{"code":4,"msg":5,"data":6},0,"success",{"doc_id":7,"user_id":8,"nickname":9,"user_avatar":10,"doc_module":4,"category_id":11,"category_name":12,"doc_title":13,"doc_description":14,"doc_content":15,"file_id":16,"file_url":17,"file_type":18,"file_size":19,"view_count":20,"is_deleted":4,"is_public":20,"is_downloadable":20,"audit_status":20,"page_count":21,"language":22,"language_code":23,"site_id":24,"html_lang":23,"table_of_contents":25,"faqs":26,"seo_title":27,"seo_description":14,"update_tm":28,"read_time":29},127258,2336475104362,"Eden","https://ap-avatar.wpscdn.com/avatar/22000c4c46a41b752dd?x-image-process=image/resize,m_fixed,w_180,h_180&k=1786595829695023868",8,"Research & Report","A Comprehensive Literature Review of Artificial Intelligence (AI) and Machine Learning (ML) - Hardware Implementation and Architectures","Artificial Intelligence (AI) and Machine Learning (ML) have rapidly expanded, driving demand for hardware architectures that deliver reliability, accuracy, and high computational capability. This thesis surveys challenges in enabling effective hardware for deep learning, where prior ASIC and FPGA solutions have often been costly and complex. The review covers ASIC and FPGA architectures and describes how application-specific techniques and optimizations can improve ML algorithm performance across deployment scenarios. It analyzes key hardware factors including memory design and computing efficiency.","\"A Comprehensive Literature Review of Artificial Intelligence (AI) and Machine Learning (ML)  \nHardware Implementation and Architectures\"  \nA Thesis submitted to the faculty of  \nSan Francisco State University  \nIn partial fulfillment of  \nthe requirements for  \nthe Degree  \nMaster of Science  \nIn  \nElectrical and Computer Engineering  \nby  \nPeter Junior Camacho  \nSan Francisco, California  \nMay 2024  \nCopyright by Peter Junior Camacho 2024  \nCertification of Approval  \nI certify that I have read A Comprehensive Literature Review of Artificial Intelligence (AI) and Machine Learning (ML) Hardware Implementation and Architectures by Peter Junior Camacho, and that in my opinion this work meets the criteria for approving a thesis submitted in partial fulfillment of the requirement for the degree Master of Science in Electrical and Computer Engineering at San Francisco State University.  \nHamid Mahmoodi, Ph.D. Professor,  \nThesis Committee Chair  \nZhuwei Qin, Ph.D. Assistant Professor  \nAbstract  \nArtificial Intelligence (AI) and Machine Learning (ML) have made a fascinating increase in popularity in recent times. This uprising suggests advancements in technology in almost all facets of life. Addressing challenges in facilitating effective hardware architectures that are reliable, accurate, and computationally powerful is at the forefront and focus of today’s innovation. Historically, hardware solutions for AI, particularly for deep learning Convolutional Neural Networks (CNNs) and Deep Neural Networks (DNNs), have been intricate and expensive, hindering the progress of such systems. This literature review will discuss Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Array (FPGA) hardware architectures including applications and techniques used to optimize ML algorithms for different deployment  \nscenarios.  \nAcknowledgements  \nI would like to acknowledge my family for their love and support while I worked towards a college degree. Everyone has played a role in getting me to this place and I hope that my younger family members will be inspired by my academic journey and will pursue their own.  \nMy sincere gratitude to the committee members, Dr. Mahmoodi and Dr. Qin. Their support with Ph.D. program applications has led to an acceptance offer with the University of California at Riverside where I will be attending Fall of 2024.  \nAnd last but not least a very special acknowledgement to Maximillian. Thank you for being by my side since the beginning of my journey at San Francisco State. You are my main supporter.  \nTable of Contents  \nList of Tables vii  \nList of Figures viii  \nI. Introduction 1  \nII. Literature Review 3  \nMethodology 7  \nSearch strategy 8  \nIII. Application Perspectives 9  \nIV. Algorithms and Techniques 12  \nV. Hardware Architectures 15  \nASIC-based Hardware 15  \nOn-chip Memory 17  \nOff-chip DRAM 17  \nNon-DRAM Design 18  \nComputing in Memory (CIM) 19  \nUse of Scaled Technology: 16 nm 21  \nCo-optimization for Improved Hardware Design 21  \nVI. FPGA-based Hardware 23  \nHard Matrix Multiplier 23  \nArria-10 GX 1150 23  \nVirtex-7 24  \nVII. Conclusion 25  \nWorks Cited 27  \nList of Tables  \nTable 1: ASIC Hardware Comparison. ......................................................................................... 22  \nList of Figures  \nFigure 1: Hardware Researched...................................................................................................... 4  \nFigure 2:Artifical Intelligence vs. Machine Learning vs. Deep Learning...................................... 9  \nFigure 3: AI Applications Used.................................................................................................... 12  \nI. Introduction  \nArtificial Intelligence (AI) is emerging as prevalent in recent times across a variety of platforms such as embedded systems to state-of-the-art applications. With this recent emergence of AI, the semiconductor industry along with researchers have been posed with a chall","cbCaibnu2dSOzg8V","https://ap.wps.com/l/cbCaibnu2dSOzg8V","pdf",480045,1,35,"English","en",105,"# List of Tables\n# List of Figures\n# I. Introduction\n# II. Literature Review\n## Methodology\n## Search strategy\n# III. Application Perspectives\n# IV. Algorithms and Techniques\n# V. Hardware Architectures\n## ASIC-based Hardware\n## On-chip Memory\n## Off-chip DRAM\n## Non-DRAM Design\n## Computing in Memory (CIM)\n## Use of Scaled Technology: 16 nm\n## Co-optimization for Improved Hardware Design\n# VI. FPGA-based Hardware\n## Hard Matrix Multiplier\n## Arria-10 GX 1150\n## Virtex-7\n# VII. Conclusion\n# Works Cited","[{\"question\":\"What hardware challenges does the thesis focus on for AI and ML?\",\"answer\":\"The thesis emphasizes designing hardware architectures that remain reliable and accurate while achieving high computational power and efficiency. It highlights factors such as power consumption, size, and performance, especially for deep neural network workloads.\"},{\"question\":\"Which hardware platforms are reviewed in the literature?\",\"answer\":\"The review covers ASIC-based and FPGA-based hardware architectures. It also discusses supporting components such as on-chip memory and off-chip DRAM along with non-DRAM design approaches.\"},{\"question\":\"What deployment scenarios and optimization aspects are addressed for ML algorithms?\",\"answer\":\"The thesis describes application-specific techniques used to optimize ML algorithms for different deployment scenarios. It also frames hardware optimization around computationally intensive operations like MAC and efficient computing strategies.\"}]","A Comprehensive Literature Review of Artificial Intelligence (AI) and Machine Learning (ML) - Hardware Implementation and Architectures | PDF",1785937786,88,{"code":4,"msg":31,"data":32},"ok",{"site_id":24,"language":23,"slug":33,"title":13,"keywords":34,"description":14,"schema_data":35,"social_meta":87,"head_meta":89,"extra_data":91,"updated_unix":28},"a-comprehensive-literature-review-of-artificial-intelligence-ai-and-machine-learning-ml-hardware-implementation-and-architectures","",{"@graph":36,"@context":86},[37,54,69],{"@type":38,"itemListElement":39},"BreadcrumbList",[40,44,48,51],{"item":41,"name":42,"@type":43,"position":20},"https://docshare.wps.com","Home","ListItem",{"item":45,"name":46,"@type":43,"position":47},"https://docshare.wps.com/document/","Document",2,{"item":49,"name":12,"@type":43,"position":50},"https://docshare.wps.com/document/research-report/",3,{"item":52,"name":13,"@type":43,"position":53},"https://docshare.wps.com/document/a-comprehensive-literature-review-of-artificial-intelligence-ai-and-machine-learning-ml-hardware-implementation-and-architectures/127258/",4,{"url":52,"name":13,"@type":55,"author":56,"headline":13,"publisher":58,"fileFormat":61,"inLanguage":23,"description":14,"dateModified":62,"datePublished":63,"encodingFormat":61,"isAccessibleForFree":64,"interactionStatistic":65},"DigitalDocument",{"name":9,"@type":57},"Person",{"url":41,"name":59,"@type":60},"DocShare","Organization","application/pdf","2026-08-22","2026-08-05",true,{"@type":66,"interactionType":67,"userInteractionCount":20},"InteractionCounter",{"@type":68},"ViewAction",{"@type":70,"mainEntity":71},"FAQPage",[72,78,82],{"name":73,"@type":74,"acceptedAnswer":75},"What hardware challenges does the thesis focus on for AI and ML?","Question",{"text":76,"@type":77},"The thesis emphasizes designing hardware architectures that remain reliable and accurate while achieving high computational power and efficiency. It highlights factors such as power consumption, size, and performance, especially for deep neural network workloads.","Answer",{"name":79,"@type":74,"acceptedAnswer":80},"Which hardware platforms are reviewed in the literature?",{"text":81,"@type":77},"The review covers ASIC-based and FPGA-based hardware architectures. It also discusses supporting components such as on-chip memory and off-chip DRAM along with non-DRAM design approaches.",{"name":83,"@type":74,"acceptedAnswer":84},"What deployment scenarios and optimization aspects are addressed for ML algorithms?",{"text":85,"@type":77},"The thesis describes application-specific techniques used to optimize ML algorithms for different deployment scenarios. It also frames hardware optimization around computationally intensive operations like MAC and efficient computing strategies.","https://schema.org",{"og:url":52,"og:type":88,"og:title":13,"og:site_name":59,"og:description":14},"article",{"robots":90,"canonical":52},"index,follow",{"doc_id":7,"site_id":24},{"code":4,"msg":5,"data":93},[94,98,102,106,111,116,121,124,129,132,136],{"id":20,"doc_module":4,"doc_module_name":46,"category_name":95,"show_sort_weight":96,"slug":97},"Story & Novel",90,"story-novel",{"id":47,"doc_module":4,"doc_module_name":46,"category_name":99,"show_sort_weight":100,"slug":101},"Literature",80,"literature",{"id":53,"doc_module":4,"doc_module_name":46,"category_name":103,"show_sort_weight":104,"slug":105},"Exam",70,"exam",{"id":107,"doc_module":4,"doc_module_name":46,"category_name":108,"show_sort_weight":109,"slug":110},5,"Comic",60,"comic",{"id":112,"doc_module":4,"doc_module_name":46,"category_name":113,"show_sort_weight":114,"slug":115},6,"Technology",50,"technology",{"id":117,"doc_module":4,"doc_module_name":46,"category_name":118,"show_sort_weight":119,"slug":120},7,"Healthcare",40,"healthcare",{"id":11,"doc_module":4,"doc_module_name":46,"category_name":12,"show_sort_weight":122,"slug":123},30,"research-report",{"id":125,"doc_module":4,"doc_module_name":46,"category_name":126,"show_sort_weight":127,"slug":128},9,"Religion & Spirituality",20,"religion-spirituality",{"id":127,"doc_module":4,"doc_module_name":46,"category_name":130,"show_sort_weight":127,"slug":131},"World Cup","world-cup",{"id":133,"doc_module":4,"doc_module_name":46,"category_name":134,"show_sort_weight":133,"slug":135},10,"Lifestyle","lifestyle",{"id":137,"doc_module":4,"doc_module_name":46,"category_name":138,"show_sort_weight":107,"slug":139},19,"General","general"]